Skip to content

Commit 87c9412

Browse files
actions-useractions-user
committed
Update Zephyr MSDK Hal based on MSDK PR: analogdevicesinc/msdk#1225 
1 parent a50f732 commit 87c9412

File tree

19 files changed

+3321
-563
lines changed

19 files changed

+3321
-563
lines changed

‎MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h‎

Lines changed: 1 addition & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -80,7 +80,7 @@ typedef struct {
8080
__IO uint32_t erfoks; /**< <tt>\b 0x18:</tt> FCR ERFOKS Register */
8181
__IO uint32_t intfl; /**< <tt>\b 0x1C:</tt> FCR INTFL Register */
8282
__IO uint32_t inten; /**< <tt>\b 0x20:</tt> FCR INTEN Register */
83-
__IO uint32_t erfoctrl; /**< <tt>\b 0x24:</tt> FCR ERFOCTRL Register */
83+
__R uint32_t rsv_0x24;
8484
__IO uint32_t frqcntctrl; /**< <tt>\b 0x28:</tt> FCR FRQCNTCTRL Register */
8585
__IO uint32_t frqcntcmp; /**< <tt>\b 0x2C:</tt> FCR FRQCNTCMP Register */
8686
__I uint32_t refclk; /**< <tt>\b 0x30:</tt> FCR REFCLK Register */
@@ -101,7 +101,6 @@ typedef struct {
101101
#define MXC_R_FCR_ERFOKS ((uint32_t)0x00000018UL) /**< Offset from FCR Base Address: <tt> 0x0018</tt> */
102102
#define MXC_R_FCR_INTFL ((uint32_t)0x0000001CUL) /**< Offset from FCR Base Address: <tt> 0x001C</tt> */
103103
#define MXC_R_FCR_INTEN ((uint32_t)0x00000020UL) /**< Offset from FCR Base Address: <tt> 0x0020</tt> */
104-
#define MXC_R_FCR_ERFOCTRL ((uint32_t)0x00000024UL) /**< Offset from FCR Base Address: <tt> 0x0024</tt> */
105104
#define MXC_R_FCR_FRQCNTCTRL ((uint32_t)0x00000028UL) /**< Offset from FCR Base Address: <tt> 0x0028</tt> */
106105
#define MXC_R_FCR_FRQCNTCMP ((uint32_t)0x0000002CUL) /**< Offset from FCR Base Address: <tt> 0x002C</tt> */
107106
#define MXC_R_FCR_REFCLK ((uint32_t)0x00000030UL) /**< Offset from FCR Base Address: <tt> 0x0030</tt> */
@@ -237,23 +236,6 @@ typedef struct {
237236

238237
/**@} end of group FCR_INTEN_Register */
239238

240-
/**
241-
* @ingroup fcr_registers
242-
* @defgroup FCR_ERFOCTRL FCR_ERFOCTRL
243-
* @brief ERFO Control Register.
244-
* @{
245-
*/
246-
#define MXC_F_FCR_ERFOCTRL_CAP_X1_POS 0 /**< ERFOCTRL_CAP_X1 Position */
247-
#define MXC_F_FCR_ERFOCTRL_CAP_X1 ((uint32_t)(0x7FUL << MXC_F_FCR_ERFOCTRL_CAP_X1_POS)) /**< ERFOCTRL_CAP_X1 Mask */
248-
249-
#define MXC_F_FCR_ERFOCTRL_CAP_X2_POS 7 /**< ERFOCTRL_CAP_X2 Position */
250-
#define MXC_F_FCR_ERFOCTRL_CAP_X2 ((uint32_t)(0x7FUL << MXC_F_FCR_ERFOCTRL_CAP_X2_POS)) /**< ERFOCTRL_CAP_X2 Mask */
251-
252-
#define MXC_F_FCR_ERFOCTRL_CAP_BYPASS_POS 14 /**< ERFOCTRL_CAP_BYPASS Position */
253-
#define MXC_F_FCR_ERFOCTRL_CAP_BYPASS ((uint32_t)(0x1UL << MXC_F_FCR_ERFOCTRL_CAP_BYPASS_POS)) /**< ERFOCTRL_CAP_BYPASS Mask */
254-
255-
/**@} end of group FCR_ERFOCTRL_Register */
256-
257239
/**
258240
* @ingroup fcr_registers
259241
* @defgroup FCR_FRQCNTCTRL FCR_FRQCNTCTRL

‎MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h‎

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -563,48 +563,48 @@ typedef struct {
563563
* @brief BTLE LDO Control Register
564564
* @{
565565
*/
566-
#define MXC_F_GCR_BTLELDOCTRL_BB_EN_POS 0 /**< BTLELDOCTRL_BB_EN Position */
567-
#define MXC_F_GCR_BTLELDOCTRL_BB_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_EN_POS)) /**< BTLELDOCTRL_BB_EN Mask */
568-
569-
#define MXC_F_GCR_BTLELDOCTRL_BB_PD_EN_POS 1 /**< BTLELDOCTRL_BB_PD_EN Position */
570-
#define MXC_F_GCR_BTLELDOCTRL_BB_PD_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_PD_EN_POS)) /**< BTLELDOCTRL_BB_PD_EN Mask */
571-
572-
#define MXC_F_GCR_BTLELDOCTRL_BB_VSEL_POS 2 /**< BTLELDOCTRL_BB_VSEL Position */
573-
#define MXC_F_GCR_BTLELDOCTRL_BB_VSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_BB_VSEL_POS)) /**< BTLELDOCTRL_BB_VSEL Mask */
574-
575-
#define MXC_F_GCR_BTLELDOCTRL_RF_EN_POS 4 /**< BTLELDOCTRL_RF_EN Position */
566+
#define MXC_F_GCR_BTLELDOCTRL_RF_EN_POS 0 /**< BTLELDOCTRL_RF_EN Position */
576567
#define MXC_F_GCR_BTLELDOCTRL_RF_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_EN_POS)) /**< BTLELDOCTRL_RF_EN Mask */
577568

578-
#define MXC_F_GCR_BTLELDOCTRL_RF_PD_EN_POS 5 /**< BTLELDOCTRL_RF_PD_EN Position */
569+
#define MXC_F_GCR_BTLELDOCTRL_RF_PD_EN_POS 1 /**< BTLELDOCTRL_RF_PD_EN Position */
579570
#define MXC_F_GCR_BTLELDOCTRL_RF_PD_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_PD_EN_POS)) /**< BTLELDOCTRL_RF_PD_EN Mask */
580571

581-
#define MXC_F_GCR_BTLELDOCTRL_RF_VSEL_POS 6 /**< BTLELDOCTRL_RF_VSEL Position */
572+
#define MXC_F_GCR_BTLELDOCTRL_RF_VSEL_POS 2 /**< BTLELDOCTRL_RF_VSEL Position */
582573
#define MXC_F_GCR_BTLELDOCTRL_RF_VSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_RF_VSEL_POS)) /**< BTLELDOCTRL_RF_VSEL Mask */
583574

584-
#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_POS 8 /**< BTLELDOCTRL_RF_BP_EN Position */
585-
#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_POS)) /**< BTLELDOCTRL_RF_BP_EN Mask */
575+
#define MXC_F_GCR_BTLELDOCTRL_BB_EN_POS 4 /**< BTLELDOCTRL_BB_EN Position */
576+
#define MXC_F_GCR_BTLELDOCTRL_BB_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_EN_POS)) /**< BTLELDOCTRL_BB_EN Mask */
586577

587-
#define MXC_F_GCR_BTLELDOCTRL_RF_DISCH_POS 9 /**< BTLELDOCTRL_RF_DISCH Position */
588-
#define MXC_F_GCR_BTLELDOCTRL_RF_DISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_DISCH_POS)) /**< BTLELDOCTRL_RF_DISCH Mask */
578+
#define MXC_F_GCR_BTLELDOCTRL_BB_PD_EN_POS 5 /**< BTLELDOCTRL_BB_PD_EN Position */
579+
#define MXC_F_GCR_BTLELDOCTRL_BB_PD_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_PD_EN_POS)) /**< BTLELDOCTRL_BB_PD_EN Mask */
589580

590-
#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_POS 10 /**< BTLELDOCTRL_BB_BP_EN Position */
581+
#define MXC_F_GCR_BTLELDOCTRL_BB_VSEL_POS 6 /**< BTLELDOCTRL_BB_VSEL Position */
582+
#define MXC_F_GCR_BTLELDOCTRL_BB_VSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_BB_VSEL_POS)) /**< BTLELDOCTRL_BB_VSEL Mask */
583+
584+
#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_POS 8 /**< BTLELDOCTRL_BB_BP_EN Position */
591585
#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_POS)) /**< BTLELDOCTRL_BB_BP_EN Mask */
592586

593-
#define MXC_F_GCR_BTLELDOCTRL_BB_DISCH_POS 11 /**< BTLELDOCTRL_BB_DISCH Position */
587+
#define MXC_F_GCR_BTLELDOCTRL_BB_DISCH_POS 9 /**< BTLELDOCTRL_BB_DISCH Position */
594588
#define MXC_F_GCR_BTLELDOCTRL_BB_DISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_DISCH_POS)) /**< BTLELDOCTRL_BB_DISCH Mask */
595589

596-
#define MXC_F_GCR_BTLELDOCTRL_BB_EN_DLY_POS 12 /**< BTLELDOCTRL_BB_EN_DLY Position */
597-
#define MXC_F_GCR_BTLELDOCTRL_BB_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_EN_DLY_POS)) /**< BTLELDOCTRL_BB_EN_DLY Mask */
590+
#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_POS 10 /**< BTLELDOCTRL_RF_BP_EN Position */
591+
#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_POS)) /**< BTLELDOCTRL_RF_BP_EN Mask */
592+
593+
#define MXC_F_GCR_BTLELDOCTRL_RF_DISCH_POS 11 /**< BTLELDOCTRL_RF_DISCH Position */
594+
#define MXC_F_GCR_BTLELDOCTRL_RF_DISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_DISCH_POS)) /**< BTLELDOCTRL_RF_DISCH Mask */
598595

599-
#define MXC_F_GCR_BTLELDOCTRL_RF_EN_DLY_POS 13 /**< BTLELDOCTRL_RF_EN_DLY Position */
596+
#define MXC_F_GCR_BTLELDOCTRL_RF_EN_DLY_POS 12 /**< BTLELDOCTRL_RF_EN_DLY Position */
600597
#define MXC_F_GCR_BTLELDOCTRL_RF_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_EN_DLY_POS)) /**< BTLELDOCTRL_RF_EN_DLY Mask */
601598

602-
#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_DLY_POS 14 /**< BTLELDOCTRL_RF_BP_EN_DLY Position */
603-
#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_DLY_POS)) /**< BTLELDOCTRL_RF_BP_EN_DLY Mask */
599+
#define MXC_F_GCR_BTLELDOCTRL_BB_EN_DLY_POS 13 /**< BTLELDOCTRL_BB_EN_DLY Position */
600+
#define MXC_F_GCR_BTLELDOCTRL_BB_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_EN_DLY_POS)) /**< BTLELDOCTRL_BB_EN_DLY Mask */
604601

605-
#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_DLY_POS 15 /**< BTLELDOCTRL_BB_BP_EN_DLY Position */
602+
#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_DLY_POS 14 /**< BTLELDOCTRL_BB_BP_EN_DLY Position */
606603
#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_DLY_POS)) /**< BTLELDOCTRL_BB_BP_EN_DLY Mask */
607604

605+
#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_DLY_POS 15 /**< BTLELDOCTRL_RF_BP_EN_DLY Position */
606+
#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_DLY_POS)) /**< BTLELDOCTRL_RF_BP_EN_DLY Mask */
607+
608608
/**@} end of group GCR_BTLELDOCTRL_Register */
609609

610610
/**

0 commit comments

Comments
 (0)