axi_ad7606x: Clean up parameters; fix clocking

There is no real need for different clocking options for this core and because
CDC is not implemented in the core, there is no way to use the EXT_CLK
parameter. Fix syntax, fix IP tcl

Signed-off-by: sarpadi <[email protected]>
(cherry picked from commit 8ce6d32)

Author: sarpadi

library/axi_ad7606x/axi_ad7606x.v

@@ -38,10 +38,8 @@
 module axi_ad7606x #(
 
   parameter ID = 0,
-  parameter DEV_CONFIG = 0,
   parameter ADC_TO_DMA_N_BITS = 16,
-  parameter ADC_N_BITS = 16,
-  parameter EXTERNAL_CLK = 0
+  parameter ADC_N_BITS = 16
 ) (
 
   // physical data interface
@@ -52,7 +50,6 @@ module axi_ad7606x #(
   output        rx_db_t,
   output        rx_rd_n,
   output        rx_wr_n,
-  input         external_clk,
 
   // physical control interface
 
@@ -142,7 +139,6 @@ module axi_ad7606x #(
   wire                  adc_dfmt_type_s[0:7];
   wire                  adc_dfmt_se_s[0:7];
 
-  wire                  adc_clk_s;
   wire [ 7:0]           adc_enable;
   wire                  adc_reset_s;
 
@@ -175,7 +171,7 @@ module axi_ad7606x #(
   wire                  m_axis_xfer_req_s;
 
   // defaults
-
+  assign adc_clk = s_axi_aclk;
   assign up_clk = s_axi_aclk;
   assign up_rstn = s_axi_aresetn;
   assign adc_reset = adc_reset_s;
@@ -216,23 +212,13 @@ module axi_ad7606x #(
     end
   end
 
-  generate
-    if (EXTERNAL_CLK == 1'b1) begin
-      assign adc_clk_s = external_clk;
-    end else begin
-      assign adc_clk_s = up_clk;
-    end
-  endgenerate
-
-  assign adc_clk = adc_clk_s;
-
   generate
     genvar i;
     for (i = 0; i < 8; i = i + 1) begin
       up_adc_channel #(
         .CHANNEL_ID(i)
       ) i_up_adc_channel (
-        .adc_clk (adc_clk_s),
+        .adc_clk (up_clk),
         .adc_rst (adc_reset_s),
         .adc_enable (adc_enable[i]),
         .adc_iqcor_enb (),
@@ -289,7 +275,7 @@ module axi_ad7606x #(
         .DATA_WIDTH (ADC_N_BITS),
         .BITS_PER_SAMPLE (ADC_TO_DMA_N_BITS)
       ) i_datafmt (
-        .clk (adc_clk),
+        .clk (up_clk),
         .valid (1'b1),
         .data (adc_data_s[k*ADC_N_BITS+(ADC_N_BITS-1):k*ADC_N_BITS]),
         .valid_out (dma_dvalid),
@@ -301,7 +287,7 @@ module axi_ad7606x #(
   endgenerate
 
   generate
-    if (DEV_CONFIG == AD7606B || DEV_CONFIG == AD7606C_16) begin
+    if (ADC_N_BITS == 16) begin
       axi_ad7606x_16b_pif i_ad7606_parallel_interface (
         .cs_n (rx_cs_n),
         .db_o (rx_db_o),
@@ -332,7 +318,7 @@ module axi_ad7606x #(
         .adc_crc_res (adc_crc_res),
         .adc_crc_err (adc_crc_err),
         .adc_valid (adc_valid),
-        .clk (adc_clk_s),
+        .clk (up_clk),
         .rstn (up_rstn),
         .adc_config_ctrl (adc_config_ctrl_s),
         .adc_ctrl_status (adc_ctrl_status_s),
@@ -372,7 +358,7 @@ module axi_ad7606x #(
         .adc_crc_res (adc_crc_res),
         .adc_crc_err (adc_crc_err),
         .adc_valid (adc_valid),
-        .clk (adc_clk_s),
+        .clk (up_clk),
         .rstn (up_rstn),
         .adc_config_ctrl (adc_config_ctrl_s),
         .adc_ctrl_status (adc_ctrl_status_s),
@@ -399,7 +385,7 @@ module axi_ad7606x #(
     .CONFIG (RD_RAW_CAP)
   ) i_up_adc_common (
     .mmcm_rst (),
-    .adc_clk (adc_clk_s),
+    .adc_clk (up_clk),
     .adc_rst (adc_reset_s),
     .adc_r1_mode (),
     .adc_ddr_edgesel (),

library/axi_ad7606x/axi_ad7606x_ip.tcl

@@ -46,60 +46,5 @@ set cc [ipx::current_core]
 set_property display_name "AXI AD7606X" $cc
 set_property description "AXI AD7606X HDL interface" $cc
 
-## define external_clk port as clock interface
-adi_add_bus external_clk slave \
-  "xilinx.com:signal:clock_rtl:1.0" \
-  "xilinx.com:signal:clock:1.0" \
-  [list {"external_clk" "CLK"} ]
-
-adi_set_ports_dependency "external_clk" \
-  "(spirit:decode(id('MODELPARAM_VALUE.EXTERNAL_CLK')) = 1)" 0
-
-## parameter validation
-
-set_property -dict [list \
-  "value_format" "bool" \
-  "value" "true" \
-  ] \
-[ipx::get_hdl_parameters EXTERNAL_CLK -of_objects $cc]
-
-## customize XGUI layout
-
-## remove the automatically generated GUI page
-
-ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc]
-ipx::save_core $cc
-
-## create a new GUI page
-
-ipgui::add_page -name {AXI AD7606X} -component $cc -display_name {AXI AD7606X}
-set page0 [ipgui::get_pagespec -name "AXI AD7606X" -component $cc]
-
-ipgui::add_param -name "EXTERNAL_CLK" -component $cc -parent $page0
-set_property -dict [list \
-  "display_name" "EXTERNAL_CLK" \
-  "tooltip" "External clock for the ADC" \
-  "widget" "checkBox" \
-] [ipgui::get_guiparamspec -name "EXTERNAL_CLK" -component $cc]
-
-ipgui::add_param -name "DEV_CONFIG" -component $cc -parent $page0
-set_property -dict [list \
-  "widget" "comboBox" \
-  "display_name" "Device Type Selection" \
-] [ipgui::get_guiparamspec -name "DEV_CONFIG" -component $cc]
-
-set_property -dict [list \
-  "value_validation_type" "pairs" \
-  "value_validation_pairs" { \
-    "AD7606B" "0" \
-    "AD7606C-16" "1" \
-    "AD7606C-18" "2" \
-  } \
-] [ipx::get_user_parameters DEV_CONFIG -of_objects $cc]
-
-adi_add_auto_fpga_spec_params
-
-## save the modifications
-
 ipx::create_xgui_files  $cc
 ipx::save_core $cc