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JESD204B support on VCK190 (#1233)
* ad9081: vck190: Added support for JESD204B ad9209: vck190: Changed serial connections and added reset signals Signed-off-by: Bogdan Luncan <[email protected]> * versal_transceiver: Fixed asymmetric modes Signed-off-by: Bogdan Luncan <[email protected]> --------- Signed-off-by: Bogdan Luncan <[email protected]>
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‎library/jesd204/jesd204_versal_gt_adapter_rx/Makefile‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,13 @@
11
####################################################################################
2-
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
2+
## Copyright (c) 2018 - 2024 Analog Devices, Inc.
33
### SPDX short identifier: BSD-1-Clause
44
## Auto-generated, do not modify!
55
####################################################################################
66

77
LIBRARY_NAME := jesd204_versal_gt_adapter_rx
88

99
GENERIC_DEPS += jesd204_versal_gt_adapter_rx.v
10+
GENERIC_DEPS += lane_align.v
1011

1112
XILINX_DEPS += ../jesd204_common/sync_header_align.v
1213
XILINX_DEPS += jesd204_versal_gt_adapter_rx_ip.tcl

‎library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v‎

Lines changed: 83 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -7,67 +7,111 @@
77

88
`timescale 1ns/100ps
99

10-
module jesd204_versal_gt_adapter_rx (
10+
module jesd204_versal_gt_adapter_rx #(
11+
parameter LINK_MODE = 2 // 1 - 8B10B, 2 - 64B66B
12+
) (
13+
// Interface to Physical Layer
1114
input [127 : 0] rxdata,
12-
input [5 : 0] rxheader,
15+
input [ 5 : 0] rxheader,
16+
input [ 15 : 0] rxctrl0,
17+
input [ 15 : 0] rxctrl1,
18+
input [ 7 : 0] rxctrl2,
19+
input [ 7 : 0] rxctrl3,
1320
output rxgearboxslip,
14-
input [1 : 0] rxheadervalid,
21+
input [ 1 : 0] rxheadervalid,
22+
output rxslide,
1523

1624
// Interface to Link layer core
17-
output [63:0] rx_data,
18-
output [1:0] rx_header,
19-
output rx_block_sync,
25+
output [ 63 : 0] rx_data,
26+
output [ 3 : 0] rx_charisk,
27+
output [ 3 : 0] rx_disperr,
28+
output [ 3 : 0] rx_notintable,
29+
output [ 1 : 0] rx_header,
30+
output rx_block_sync,
31+
input en_char_align,
2032

21-
input usr_clk
33+
input usr_clk
2234
);
2335

24-
wire rxgearboxslip_s;
2536
reg [63:0] rxdata_d;
2637
reg [ 1:0] rxheader_d;
2738
reg rxgearboxslip_d;
2839
reg [ 1:0] rxheadervalid_d;
40+
reg [15:0] rxctrl0_d;
41+
reg [15:0] rxctrl1_d;
42+
reg [ 7:0] rxctrl3_d;
43+
wire rxgearboxslip_s;
2944

3045
always @(posedge usr_clk) begin
3146
rxdata_d <= rxdata[63:0];
3247
rxheader_d <= rxheader[1:0];
3348
rxgearboxslip_d <= rxgearboxslip_s;
49+
rxheadervalid_d <= rxheadervalid;
50+
rxctrl0_d <= rxctrl0;
51+
rxctrl1_d <= rxctrl1;
52+
rxctrl3_d <= rxctrl3;
3453
end
3554

36-
// Sync header alignment
37-
wire rx_bitslip_req_s;
38-
reg [5:0] rx_bitslip_done_cnt = 'h0;
39-
always @(posedge usr_clk) begin
40-
if (rx_bitslip_done_cnt[5]) begin
41-
rx_bitslip_done_cnt <= 'b0;
42-
end else if (rx_bitslip_req_s & ~rx_bitslip_done_cnt[5]) begin
43-
rx_bitslip_done_cnt <= rx_bitslip_done_cnt + 1;
55+
generate if (LINK_MODE == 2) begin
56+
// Sync header alignment
57+
wire rx_bitslip_req_s;
58+
reg [5:0] rx_bitslip_done_cnt = 'h0;
59+
always @(posedge usr_clk) begin
60+
if (rx_bitslip_done_cnt[5]) begin
61+
rx_bitslip_done_cnt <= 'b0;
62+
end else if (rx_bitslip_req_s & ~rx_bitslip_done_cnt[5]) begin
63+
rx_bitslip_done_cnt <= rx_bitslip_done_cnt + 1;
64+
end
4465
end
45-
end
4666

47-
reg rx_bitslip_req_s_d = 1'b0;
48-
always @(posedge usr_clk) begin
49-
rx_bitslip_req_s_d <= rx_bitslip_req_s;
50-
end
67+
reg rx_bitslip_req_s_d = 1'b0;
68+
always @(posedge usr_clk) begin
69+
rx_bitslip_req_s_d <= rx_bitslip_req_s;
70+
end
5171

52-
assign rxgearboxslip_s = rx_bitslip_req_s & ~rx_bitslip_req_s_d;
53-
assign rxgearboxslip = rxgearboxslip_d;
72+
assign rxgearboxslip_s = rx_bitslip_req_s & ~rx_bitslip_req_s_d;
73+
assign rxgearboxslip = rxgearboxslip_d;
5474

55-
wire [63:0] rxdata_flip;
56-
genvar i;
57-
for (i = 0; i < 64; i=i+1) begin
58-
assign rxdata_flip[63-i] = rxdata_d[i];
59-
end
75+
wire [63:0] rxdata_flip;
76+
wire [ 1:0] rxheader_flip;
77+
genvar i;
78+
for (i = 0; i < 64; i=i+1) begin
79+
assign rxdata_flip[63-i] = rxdata_d[i];
80+
end
81+
assign rxheader_flip = {rxheader_d[0], rxheader_d[1]};
82+
83+
// Sync header alignment
84+
sync_header_align i_sync_header_align (
85+
.clk(usr_clk),
86+
.reset(~rxheadervalid_d[0]),
87+
// Flip header bits and data
88+
.i_data({rxheader_flip, rxdata_flip}),
89+
.i_slip(rx_bitslip_req_s),
90+
.i_slip_done(rx_bitslip_done_cnt[5]),
91+
.o_data(rx_data),
92+
.o_header(rx_header),
93+
.o_block_sync(rx_block_sync));
6094

61-
// Sync header alignment
62-
sync_header_align i_sync_header_align (
63-
.clk(usr_clk),
64-
.reset(~rxheadervalid[0]),
65-
// Flip header bits and data
66-
.i_data({rxheader_d[0],rxheader_d[1],rxdata_flip[63:0]}),
67-
.i_slip(rx_bitslip_req_s),
68-
.i_slip_done(rx_bitslip_done_cnt[5]),
69-
.o_data(rx_data),
70-
.o_header(rx_header),
71-
.o_block_sync(rx_block_sync));
95+
assign rx_disperr = 4'b0;
96+
assign rx_charisk = 4'b0;
97+
assign rx_notintable = 4'b0;
98+
assign rxslide = 1'b0;
99+
end else begin
100+
assign rx_data = {32'b0, rxdata_d[31:0]};
101+
assign rx_header = rxheader_d[1:0];
102+
103+
assign rx_charisk = rxctrl0_d[3:0];
104+
assign rx_disperr = rxctrl1_d[3:0];
105+
assign rx_notintable = rxctrl3_d[3:0];
106+
assign rx_block_sync = 1'b0;
107+
assign rxgearboxslip = 1'b0;
108+
109+
lane_align i_lane_align (
110+
.usr_clk (usr_clk),
111+
.rxdata (rxdata_d[31:0]),
112+
.rx_slide (rxslide),
113+
.en_char_align (en_char_align));
114+
end
115+
endgenerate
72116

73117
endmodule

‎library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.tcl‎

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
###############################################################################
2-
## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2017-2024 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIJESD204
44
###############################################################################
55

@@ -9,6 +9,7 @@ source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
99
adi_ip_create jesd204_versal_gt_adapter_rx
1010
adi_ip_files jesd204_versal_gt_adapter_rx [list \
1111
jesd204_versal_gt_adapter_rx.v \
12+
lane_align.v \
1213
../jesd204_common/sync_header_align.v \
1314
]
1415

@@ -23,6 +24,9 @@ adi_add_bus "RX" "master" \
2324
{ \
2425
{ "rx_data" "rxdata" } \
2526
{ "rx_header" "rxheader" } \
27+
{ "rx_charisk" "rxcharisk"} \
28+
{ "rx_disperr" "rxdisperr"} \
29+
{ "rx_notintable" "rxnotintable"} \
2630
{ "rx_block_sync" "rxblock_sync" } \
2731
}
2832

@@ -32,6 +36,11 @@ adi_add_bus "RX_GT_IP_Interface" "master" \
3236
{ \
3337
{ "rxdata" "ch_rxdata" } \
3438
{ "rxheader" "ch_rxheader" } \
39+
{ "rxctrl0" "ch_rxctrl0" } \
40+
{ "rxctrl1" "ch_rxctrl1" } \
41+
{ "rxctrl2" "ch_rxctrl2" } \
42+
{ "rxctrl3" "ch_rxctrl3" } \
43+
{ "rxslide" "ch_rxslide" } \
3544
{ "rxheadervalid" "ch_rxheadervalid" } \
3645
{ "rxgearboxslip" "ch_rxgearboxslip" } \
3746
}

‎library/jesd204/jesd204_versal_gt_adapter_rx/lane_align.v‎

Lines changed: 90 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,90 @@
1+
// ***************************************************************************
2+
// ***************************************************************************
3+
// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
4+
// SPDX short identifier: ADIJESD204
5+
// ***************************************************************************
6+
// ***************************************************************************
7+
8+
module lane_align (
9+
input usr_clk,
10+
input [31:0] rxdata,
11+
input en_char_align,
12+
output rx_slide
13+
);
14+
15+
localparam K_CHARACTER = 32'hBCBCBCBC;
16+
17+
localparam WAIT_FOR_CHAR_ALIGN = 0;
18+
localparam CHECK_ALIGNMENT = 1;
19+
localparam PULSE_SLIDE = 2;
20+
localparam WAIT_DELAY = 3;
21+
22+
reg [2:0] state = WAIT_FOR_CHAR_ALIGN;
23+
reg [2:0] next_state;
24+
reg [5:0] counter = 0;
25+
reg [5:0] next_counter;
26+
reg en_char_align_d1;
27+
reg en_char_align_d2;
28+
wire en_char_align_edge;
29+
wire rx_slide_s;
30+
31+
always @(posedge usr_clk) begin
32+
en_char_align_d2 <= en_char_align;
33+
en_char_align_d1 <= en_char_align_d2;
34+
end
35+
36+
assign en_char_align_edge = ~en_char_align_d2 & ~en_char_align_d1 & en_char_align;
37+
38+
always @(posedge usr_clk) begin
39+
if (en_char_align_edge) begin
40+
state <= CHECK_ALIGNMENT;
41+
counter <= 'd0;
42+
end else begin
43+
state <= next_state;
44+
counter <= next_counter;
45+
end
46+
end
47+
48+
always @(*) begin
49+
next_counter <= counter;
50+
case (state)
51+
WAIT_FOR_CHAR_ALIGN: begin
52+
if (en_char_align) begin
53+
next_state <= CHECK_ALIGNMENT;
54+
end else begin
55+
next_state <= WAIT_FOR_CHAR_ALIGN;
56+
end
57+
end
58+
CHECK_ALIGNMENT: begin
59+
if (rxdata == K_CHARACTER) begin
60+
next_state <= WAIT_FOR_CHAR_ALIGN;
61+
end else begin
62+
next_counter <= 'd0;
63+
next_state <= PULSE_SLIDE;
64+
end
65+
end
66+
PULSE_SLIDE: begin // a pulse is valid only if it takes 2 usr_clk cycles
67+
if (counter == 'd1) begin
68+
next_state <= WAIT_DELAY;
69+
next_counter <= 'd0;
70+
end else begin
71+
next_state <= PULSE_SLIDE;
72+
next_counter <= counter + 1'b1;
73+
end
74+
end
75+
WAIT_DELAY: begin // wait 32 usr_clk cycles between each pulse
76+
if (counter[5]) begin
77+
next_state <= CHECK_ALIGNMENT;
78+
end else begin
79+
next_state <= WAIT_DELAY;
80+
next_counter <= counter + 1'b1;
81+
end
82+
end
83+
endcase
84+
end
85+
86+
assign rx_slide_s = (state == PULSE_SLIDE)? 1'b1 : 1'b0;
87+
88+
assign rx_slide = rx_slide_s;
89+
90+
endmodule

‎library/jesd204/jesd204_versal_gt_adapter_tx/Makefile‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
####################################################################################
2-
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
2+
## Copyright (c) 2018 - 2024 Analog Devices, Inc.
33
### SPDX short identifier: BSD-1-Clause
44
## Auto-generated, do not modify!
55
####################################################################################

‎library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.v‎

Lines changed: 42 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -7,27 +7,55 @@
77

88
`timescale 1ns/100ps
99

10-
module jesd204_versal_gt_adapter_tx (
11-
output reg [127 : 0] txdata,
12-
output reg [5 : 0] txheader,
13-
10+
module jesd204_versal_gt_adapter_tx #(
11+
parameter LINK_MODE = 2 // 1 - 8B10B, 2 - 64B66B
12+
) (
13+
output [127 : 0] txdata,
14+
output [ 5 : 0] txheader,
15+
output [ 15 : 0] txctrl0,
16+
output [ 15 : 0] txctrl1,
17+
output [ 7 : 0] txctrl2,
1418
// Interface to Link layer core
15-
input [63:0] tx_data,
16-
input [1:0] tx_header,
19+
input [ 63 : 0] tx_data,
20+
input [ 1 : 0] tx_header,
21+
input [ 3 : 0] tx_charisk,
1722

1823
input usr_clk
1924
);
2025

21-
wire [63:0] tx_data_flip;
22-
genvar i;
23-
for (i = 0; i < 64; i=i+1) begin
24-
assign tx_data_flip[63-i] = tx_data[i];
25-
end
26+
reg [63:0] txdata_d;
27+
reg [ 1:0] txheader_d;
28+
reg [ 3:0] txcharisk_d;
2629

27-
// Flip header bits and data
2830
always @(posedge usr_clk) begin
29-
txdata <= {64'b0, tx_data_flip};
30-
txheader <= {4'b0, tx_header[0], tx_header[1]};
31+
txdata_d <= tx_data;
32+
txheader_d <= tx_header;
33+
txcharisk_d <= tx_charisk;
34+
end
35+
36+
generate if (LINK_MODE == 2) begin
37+
wire [63:0] tx_data_flip;
38+
wire [ 1:0] tx_header_flip;
39+
genvar i;
40+
for (i = 0; i < 64; i=i+1) begin
41+
assign tx_data_flip[63-i] = txdata_d[i];
42+
end
43+
assign tx_header_flip = {txheader_d[0], txheader_d[1]};
44+
45+
// Flip header bits and data
46+
assign txdata = {64'b0, tx_data_flip};
47+
assign txheader = {4'b0, tx_header_flip};
48+
49+
assign txctrl0 = 16'b0;
50+
assign txctrl1 = 16'b0;
51+
assign txctrl2 = 16'b0;
52+
end else begin
53+
assign txdata = {96'b0, txdata_d[31:0]};
54+
assign txheader = {4'b0, txheader_d};
55+
assign txctrl2 = {4'b0, txcharisk_d};
56+
assign txctrl0 = 16'b0;
57+
assign txctrl1 = 16'b0;
3158
end
59+
endgenerate
3260

3361
endmodule

‎library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ip.tcl‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
###############################################################################
2-
## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2017-2024 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIJESD204
44
###############################################################################
55

@@ -22,6 +22,9 @@ adi_add_bus "TX_GT_IP_Interface" "master" \
2222
{ \
2323
{ "txdata" "ch_txdata" } \
2424
{ "txheader" "ch_txheader" } \
25+
{ "txctrl0" "ch_txctrl0" } \
26+
{ "txctrl1" "ch_txctrl1" } \
27+
{ "txctrl2" "ch_txctrl2" } \
2528
}
2629

2730
adi_add_bus "TX" "slave" \
@@ -30,6 +33,7 @@ adi_add_bus "TX" "slave" \
3033
{ \
3134
{ "tx_data" "txdata" } \
3235
{ "tx_header" "txheader" } \
36+
{ "tx_charisk" "txcharisk" } \
3337
}
3438

3539
ipx::save_core [ipx::current_core]

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