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AndrDragomirbia1708
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adrv9026: Add vck190 support
Signed-off-by: AndrDragomir <[email protected]>
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docs/projects/adrv9026/index.rst

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@@ -33,6 +33,9 @@ Supported carriers
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* -
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- :xilinx:`ZCU102`
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- FMC HPC1
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* -
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- :xilinx:`VCK190`
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- FMCP1
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Block design
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-------------------------------------------------------------------------------
@@ -85,9 +88,8 @@ for each project.
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**system_project.tcl** file, located in
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hdl/projects/adrv9026/$CARRIER/system_project.tcl
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.. warning::
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``Lane Rate = I/Q Sample Rate x M x N' x (10 \ 8) \ L``
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.. math::
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Lane Rate = Sample Rate*\frac{M}{L}*N'* \frac{10}{8}
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The following are the parameters of this project that can be configured:
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@@ -117,18 +119,18 @@ CPU/Memory interconnects addresses
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The addresses are dependent on the architecture of the FPGA, having an offset
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added to the base address from HDL (see more at :ref:`architecture`).
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==================== ===========
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Instance ZynqMP
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==================== ===========
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axi_adrv9026_tx_jesd 0x84A90000
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axi_adrv9026_rx_jesd 0x84AA0000
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axi_adrv9026_tx_dma 0x9c420000
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axi_adrv9026_rx_dma 0x9c400000
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tx_adrv9026_tpl_core 0x84A04000
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rx_adrv9026_tpl_core 0x84A00000
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axi_adrv9026_tx_xcvr 0x84A80000
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axi_adrv9026_rx_xcvr 0x84A60000
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==================== ===========
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==================== =========== ===========
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Instance ZynqMP Versal
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==================== =========== ===========
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axi_adrv9026_tx_jesd 0x84A90000 0xA4A90000
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axi_adrv9026_rx_jesd 0x84AA0000 0xA4AA0000
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axi_adrv9026_tx_dma 0x9c420000 0xBC420000
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axi_adrv9026_rx_dma 0x9c400000 0xBC400000
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tx_adrv9026_tpl_core 0x84A04000 0xA4A04000
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rx_adrv9026_tpl_core 0x84A00000 0xA4A00000
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axi_adrv9026_tx_xcvr 0x84A80000 0xA4A80000
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axi_adrv9026_rx_xcvr 0x84A60000 0xA4A60000
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==================== =========== ===========
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SPI connections
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -282,34 +284,32 @@ location and run the make command by typing in your command prompt:
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The following dropdowns contain tables with the parameters that can be used to
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configure this project, depending on the carrier used.
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Where a cell contains a --- (dash) it means that the parameter doesn't exist
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for that project (adrv9026/carrier or adrv9026/carrier).
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.. collapsible:: Default values of the ``make`` parameters for ADRV9026
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.. collapsible:: Default values of the make parameters for ADRV9026
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+-------------------+------------------------------------------------------+
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| Parameter | Default value of the parameters depending on carrier |
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+-------------------+---------------------------+--------------------------+
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| | A10SoC | ZCU102 |
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+===================+===========================+==========================+
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| JESD_MODE | 8B10B | 8B10B |
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+-------------------+---------------------------+--------------------------+
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| RX_LANE_RATE | 10 | 10 |
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+-------------------+---------------------------+--------------------------+
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| TX_LANE_RATE | 10 | 10 |
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+-------------------+---------------------------+--------------------------+
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| RX_JESD_M | 8 | 8 |
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+-------------------+---------------------------+--------------------------+
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| RX_JESD_L | 4 | 4 |
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+-------------------+---------------------------+--------------------------+
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| RX_JESD_S | 1 | 1 |
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+-------------------+---------------------------+--------------------------+
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| TX_JESD_M | 8 | 8 |
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+-------------------+---------------------------+--------------------------+
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| TX_JESD_L | 4 | 4 |
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+-------------------+---------------------------+--------------------------+
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| TX_JESD_S | 1 | 1 |
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+-------------------+---------------------------+--------------------------+
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+-------------------+------------------+----------------+------------------+
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| | A10SoC | ZCU102 | VCK190 |
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+===================+==================+================+==================+
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| JESD_MODE | 8B10B | 8B10B | 8B10B |
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+-------------------+------------------+----------------+------------------+
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| RX_LANE_RATE | 10 | 10 | 10 |
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+-------------------+------------------+----------------+------------------+
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| TX_LANE_RATE | 10 | 10 | 10 |
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+-------------------+------------------+----------------+------------------+
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| RX_JESD_M | 8 | 8 | 8 |
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+-------------------+------------------+----------------+------------------+
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| RX_JESD_L | 4 | 4 | 4 |
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+-------------------+------------------+----------------+------------------+
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| RX_JESD_S | 1 | 1 | 1 |
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+-------------------+------------------+----------------+------------------+
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| TX_JESD_M | 8 | 8 | 8 |
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+-------------------+------------------+----------------+------------------+
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| TX_JESD_L | 4 | 4 | 4 |
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+-------------------+------------------+----------------+------------------+
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| TX_JESD_S | 1 | 1 | 1 |
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+-------------------+------------------+----------------+------------------+
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A more comprehensive build guide can be found in the :ref:`build_hdl` user guide.
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