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iio: adc: ad4170-4: Add GPIO controller support
The AD4170-4 has four multifunctional pins that can be used as GPIOs. The GPIO functionality can be accessed when the AD4170-4 chip is not busy performing continuous data capture or handling any other register read/write request. Also, the AD4170-4 does not provide any interrupt based on GPIO pin states so AD4170-4 GPIOs can't be used as interrupt sources. Implement gpio_chip callbacks to make AD4170-4 GPIO pins controllable through the gpiochip interface. [marcelo.schmitt@analog.com: Adapted with 6.12 backport needed changes] Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com> Link: https://patch.msgid.link/e031189d4b7e20cf02dd13220ab1ddf4798760c2.1751895245.git.marcelo.schmitt@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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‎drivers/iio/adc/Kconfig‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -98,6 +98,7 @@ config AD4170_4
9898
select IIO_BUFFER
9999
select IIO_TRIGGERED_BUFFER
100100
depends on COMMON_CLK
101+
depends on GPIOLIB
101102
help
102103
Say yes here to build support for Analog Devices AD4170-4 SPI analog
103104
to digital converters (ADC).

‎drivers/iio/adc/ad4170-4.c‎

Lines changed: 226 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,7 @@
1818
#include <linux/delay.h>
1919
#include <linux/device.h>
2020
#include <linux/err.h>
21+
#include <linux/gpio/driver.h>
2122
#include <linux/iio/buffer.h>
2223
#include <linux/iio/iio.h>
2324
#include <linux/iio/trigger.h>
@@ -68,6 +69,9 @@
6869
#define AD4170_FILTER_FS_REG(x) (0xC7 + 14 * (x))
6970
#define AD4170_OFFSET_REG(x) (0xCA + 14 * (x))
7071
#define AD4170_GAIN_REG(x) (0xCD + 14 * (x))
72+
#define AD4170_GPIO_MODE_REG 0x191
73+
#define AD4170_GPIO_OUTPUT_REG 0x193
74+
#define AD4170_GPIO_INPUT_REG 0x195
7175
#define AD4170_ADC_CTRL_CONT_READ_EXIT_REG 0x200 /* virtual reg */
7276

7377
#define AD4170_REG_READ_MASK BIT(14)
@@ -106,6 +110,12 @@
106110
/* AD4170_FILTER_REG */
107111
#define AD4170_FILTER_FILTER_TYPE_MSK GENMASK(3, 0)
108112

113+
/* AD4170_GPIO_MODE_REG */
114+
#define AD4170_GPIO_MODE_GPIO0_MSK GENMASK(1, 0)
115+
#define AD4170_GPIO_MODE_GPIO1_MSK GENMASK(3, 2)
116+
#define AD4170_GPIO_MODE_GPIO2_MSK GENMASK(5, 4)
117+
#define AD4170_GPIO_MODE_GPIO3_MSK GENMASK(7, 6)
118+
109119
/* AD4170 register constants */
110120

111121
/* AD4170_CLOCK_CTRL_REG constants */
@@ -146,9 +156,14 @@
146156
#define AD4170_FILTER_FILTER_TYPE_SINC5 0x4
147157
#define AD4170_FILTER_FILTER_TYPE_SINC3 0x6
148158

159+
/* AD4170_GPIO_MODE_REG constants */
160+
#define AD4170_GPIO_MODE_GPIO_INPUT 1
161+
#define AD4170_GPIO_MODE_GPIO_OUTPUT 2
162+
149163
/* Device properties and auxiliary constants */
150164

151165
#define AD4170_NUM_ANALOG_PINS 9
166+
#define AD4170_NUM_GPIO_PINS 4
152167
#define AD4170_MAX_ADC_CHANNELS 16
153168
#define AD4170_MAX_IIO_CHANNELS (AD4170_MAX_ADC_CHANNELS + 1)
154169
#define AD4170_MAX_ANALOG_PINS 8
@@ -177,6 +192,9 @@
177192

178193
#define AD4170_ADC_CTRL_CONT_READ_EXIT 0xA5
179194

195+
/* GPIO pin functions */
196+
#define AD4170_GPIO_UNASSIGNED 0x00
197+
180198
static const unsigned int ad4170_reg_size[] = {
181199
[AD4170_CONFIG_A_REG] = 1,
182200
[AD4170_DATA_24B_REG] = 3,
@@ -214,6 +232,9 @@ static const unsigned int ad4170_reg_size[] = {
214232
[AD4170_OFFSET_REG(5) ... AD4170_GAIN_REG(5)] = 3,
215233
[AD4170_OFFSET_REG(6) ... AD4170_GAIN_REG(6)] = 3,
216234
[AD4170_OFFSET_REG(7) ... AD4170_GAIN_REG(7)] = 3,
235+
[AD4170_GPIO_MODE_REG] = 2,
236+
[AD4170_GPIO_OUTPUT_REG] = 2,
237+
[AD4170_GPIO_INPUT_REG] = 2,
217238
[AD4170_ADC_CTRL_CONT_READ_EXIT_REG] = 0,
218239
};
219240

@@ -365,6 +386,8 @@ struct ad4170_state {
365386
struct clk_hw int_clk_hw;
366387
unsigned int clock_ctrl;
367388
unsigned int pins_fn[AD4170_NUM_ANALOG_PINS];
389+
int gpio_fn[AD4170_NUM_GPIO_PINS];
390+
struct gpio_chip gpiochip;
368391
/*
369392
* DMA (thus cache coherency maintenance) requires the transfer buffers
370393
* to live in their own cache lines.
@@ -1475,6 +1498,197 @@ static int ad4170_soft_reset(struct ad4170_state *st)
14751498
return 0;
14761499
}
14771500

1501+
static int ad4170_gpio_get(struct gpio_chip *gc, unsigned int offset)
1502+
{
1503+
struct iio_dev *indio_dev = gpiochip_get_data(gc);
1504+
struct ad4170_state *st = iio_priv(indio_dev);
1505+
unsigned int val;
1506+
int ret;
1507+
1508+
if (!iio_device_claim_direct(indio_dev))
1509+
return -EBUSY;
1510+
1511+
ret = regmap_read(st->regmap, AD4170_GPIO_MODE_REG, &val);
1512+
if (ret)
1513+
goto err_release;
1514+
1515+
/*
1516+
* If the GPIO is configured as an input, read the current value from
1517+
* AD4170_GPIO_INPUT_REG. Otherwise, read the input value from
1518+
* AD4170_GPIO_OUTPUT_REG.
1519+
*/
1520+
if (val & BIT(offset * 2))
1521+
ret = regmap_read(st->regmap, AD4170_GPIO_INPUT_REG, &val);
1522+
else
1523+
ret = regmap_read(st->regmap, AD4170_GPIO_OUTPUT_REG, &val);
1524+
if (ret)
1525+
goto err_release;
1526+
1527+
ret = !!(val & BIT(offset));
1528+
err_release:
1529+
iio_device_release_direct(indio_dev);
1530+
1531+
return ret;
1532+
}
1533+
1534+
static void ad4170_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
1535+
{
1536+
struct iio_dev *indio_dev = gpiochip_get_data(gc);
1537+
struct ad4170_state *st = iio_priv(indio_dev);
1538+
int ret;
1539+
1540+
if (!iio_device_claim_direct(indio_dev)) {
1541+
dev_err(&st->spi->dev, "failed to set GPIO: %d", -EBUSY);
1542+
return;
1543+
}
1544+
1545+
if (!!value)
1546+
ret = regmap_set_bits(st->regmap, AD4170_GPIO_OUTPUT_REG, BIT(offset));
1547+
else
1548+
ret = regmap_clear_bits(st->regmap, AD4170_GPIO_OUTPUT_REG, BIT(offset));
1549+
1550+
iio_device_release_direct(indio_dev);
1551+
if (ret)
1552+
dev_err(&st->spi->dev, "failed to set GPIO: %d", ret);
1553+
}
1554+
1555+
static int ad4170_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
1556+
{
1557+
struct iio_dev *indio_dev = gpiochip_get_data(gc);
1558+
struct ad4170_state *st = iio_priv(indio_dev);
1559+
unsigned int val;
1560+
int ret;
1561+
1562+
if (!iio_device_claim_direct(indio_dev))
1563+
return -EBUSY;
1564+
1565+
ret = regmap_read(st->regmap, AD4170_GPIO_MODE_REG, &val);
1566+
if (ret)
1567+
goto err_release;
1568+
1569+
if (val & BIT(offset * 2 + 1))
1570+
ret = GPIO_LINE_DIRECTION_OUT;
1571+
else
1572+
ret = GPIO_LINE_DIRECTION_IN;
1573+
1574+
err_release:
1575+
iio_device_release_direct(indio_dev);
1576+
1577+
return ret;
1578+
}
1579+
1580+
static int ad4170_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
1581+
{
1582+
struct iio_dev *indio_dev = gpiochip_get_data(gc);
1583+
struct ad4170_state *st = iio_priv(indio_dev);
1584+
unsigned long gpio_mask;
1585+
int ret;
1586+
1587+
if (!iio_device_claim_direct(indio_dev))
1588+
return -EBUSY;
1589+
1590+
switch (offset) {
1591+
case 0:
1592+
gpio_mask = AD4170_GPIO_MODE_GPIO0_MSK;
1593+
break;
1594+
case 1:
1595+
gpio_mask = AD4170_GPIO_MODE_GPIO1_MSK;
1596+
break;
1597+
case 2:
1598+
gpio_mask = AD4170_GPIO_MODE_GPIO2_MSK;
1599+
break;
1600+
case 3:
1601+
gpio_mask = AD4170_GPIO_MODE_GPIO3_MSK;
1602+
break;
1603+
default:
1604+
ret = -EINVAL;
1605+
goto err_release;
1606+
}
1607+
ret = regmap_update_bits(st->regmap, AD4170_GPIO_MODE_REG, gpio_mask,
1608+
AD4170_GPIO_MODE_GPIO_INPUT << (2 * offset));
1609+
1610+
err_release:
1611+
iio_device_release_direct(indio_dev);
1612+
1613+
return ret;
1614+
}
1615+
1616+
static int ad4170_gpio_direction_output(struct gpio_chip *gc,
1617+
unsigned int offset, int value)
1618+
{
1619+
struct iio_dev *indio_dev = gpiochip_get_data(gc);
1620+
struct ad4170_state *st = iio_priv(indio_dev);
1621+
unsigned long gpio_mask;
1622+
int ret;
1623+
1624+
ad4170_gpio_set(gc, offset, value);
1625+
1626+
if (!iio_device_claim_direct(indio_dev))
1627+
return -EBUSY;
1628+
1629+
switch (offset) {
1630+
case 0:
1631+
gpio_mask = AD4170_GPIO_MODE_GPIO0_MSK;
1632+
break;
1633+
case 1:
1634+
gpio_mask = AD4170_GPIO_MODE_GPIO1_MSK;
1635+
break;
1636+
case 2:
1637+
gpio_mask = AD4170_GPIO_MODE_GPIO2_MSK;
1638+
break;
1639+
case 3:
1640+
gpio_mask = AD4170_GPIO_MODE_GPIO3_MSK;
1641+
break;
1642+
default:
1643+
ret = -EINVAL;
1644+
goto err_release;
1645+
}
1646+
ret = regmap_update_bits(st->regmap, AD4170_GPIO_MODE_REG, gpio_mask,
1647+
AD4170_GPIO_MODE_GPIO_OUTPUT << (2 * offset));
1648+
1649+
err_release:
1650+
iio_device_release_direct(indio_dev);
1651+
1652+
return ret;
1653+
}
1654+
1655+
static int ad4170_gpio_init_valid_mask(struct gpio_chip *gc,
1656+
unsigned long *valid_mask,
1657+
unsigned int ngpios)
1658+
{
1659+
struct ad4170_state *st = gpiochip_get_data(gc);
1660+
unsigned int i;
1661+
1662+
/* Only expose GPIOs that were not assigned any other function. */
1663+
for (i = 0; i < ngpios; i++) {
1664+
bool valid = st->gpio_fn[i] == AD4170_GPIO_UNASSIGNED;
1665+
1666+
__assign_bit(i, valid_mask, valid);
1667+
}
1668+
1669+
return 0;
1670+
}
1671+
1672+
static int ad4170_gpio_init(struct iio_dev *indio_dev)
1673+
{
1674+
struct ad4170_state *st = iio_priv(indio_dev);
1675+
1676+
st->gpiochip.label = "ad4170_gpios";
1677+
st->gpiochip.base = -1;
1678+
st->gpiochip.ngpio = AD4170_NUM_GPIO_PINS;
1679+
st->gpiochip.parent = &st->spi->dev;
1680+
st->gpiochip.can_sleep = true;
1681+
st->gpiochip.init_valid_mask = ad4170_gpio_init_valid_mask;
1682+
st->gpiochip.get_direction = ad4170_gpio_get_direction;
1683+
st->gpiochip.direction_input = ad4170_gpio_direction_input;
1684+
st->gpiochip.direction_output = ad4170_gpio_direction_output;
1685+
st->gpiochip.get = ad4170_gpio_get;
1686+
st->gpiochip.set = ad4170_gpio_set;
1687+
st->gpiochip.owner = THIS_MODULE;
1688+
1689+
return devm_gpiochip_add_data(&st->spi->dev, &st->gpiochip, indio_dev);
1690+
}
1691+
14781692
static int ad4170_parse_reference(struct ad4170_state *st,
14791693
struct fwnode_handle *child,
14801694
struct ad4170_setup *setup)
@@ -1818,7 +2032,18 @@ static int ad4170_parse_firmware(struct iio_dev *indio_dev)
18182032
if (ret)
18192033
return ret;
18202034

1821-
return ad4170_parse_channels(indio_dev);
2035+
ret = ad4170_parse_channels(indio_dev);
2036+
if (ret)
2037+
return ret;
2038+
2039+
/* Only create a GPIO chip if flagged for it */
2040+
if (device_property_read_bool(dev, "gpio-controller")) {
2041+
ret = ad4170_gpio_init(indio_dev);
2042+
if (ret)
2043+
return ret;
2044+
}
2045+
2046+
return 0;
18222047
}
18232048

18242049
static int ad4170_initial_config(struct iio_dev *indio_dev)

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