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microblaze: dts: vcu118_quad_ad9084: Add external primary/second board DTS variants
Add DTS files for VCU118 quad AD9084 RevB external primary and second board configurations, for both default and 26.4 GHz lane rate profiles. These override the adf4030 node and configure JESD204 FSM stop states. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
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‎arch/microblaze/boot/dts/vcu118_quad_ad9084_26p4_revB_ext_primary.dts‎

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Analog Devices Quad-AD9084 RevB
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* https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9084
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* https://wiki.analog.com/resources/eval/user-guides/ad9084_fmca_ebz/ad9084_fmca_ebz_hdl
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*
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* hdl_project: <quad_apollo/vcu118>
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* board_revision: <Rev.B>
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*
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* Copyright (C) 2024 Analog Devices Inc.
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*/
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#define DEVICE_PROFILE_NAME "id01_uc43.bin"
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#define MHz 1000000
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#define FREQ_J1_MHz (400 * MHz)
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#define TX_CORE_CLK_MHz (400 * MHz)
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#define RX_CORE_CLK_MHz (400 * MHz)
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#define FPGA_REFCLK_CLK_MHz (400 * MHz)
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#define SYSREF_CLK_MHz (2 * 6250000)
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#include "vcu118_quad_ad9084_revB.dts"
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#include <dt-bindings/jesd204/device-states.h>
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&axi_ethernet {
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local-mac-address = [00 0a 35 00 90 84];
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};
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&axi_spi_2 {
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/delete-node/ adf4030;
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adf4030: adf4030@4 {
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#clock-cells = <1>;
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compatible = "adi,adf4030";
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reg = <4>;
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#address-cells = <1>;
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#size-cells = <0>;
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#io-channel-cells = <1>;
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spi-max-frequency = <1000000>;
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clocks = <&ltc6952 5>;
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clock-names = "refin";
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clock-output-names = "adf4030_bsync_0", "adf4030_bsync_1",
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"adf4030_bsync_2", "adf4030_bsync_3", "adf4030_bsync_4",
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"adf4030_bsync_5", "adf4030_bsync_6", "adf4030_bsync_7",
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"adf4030_bsync_8", "adf4030_bsync_9";
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label = "adf4030";
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jesd204-device;
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#jesd204-cells = <2>;
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jesd204-sysref-provider;
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adi,vco-frequency-hz = <2500000000>; /* 2.5 GHz */
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adi,bsync-frequency-hz = <SYSREF_CLK_MHz>;
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adi,bsync-autoalign-reference-channel = <9>; /* J46_J47_UFL */
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adi,bsync-autoalign-iteration-count = <6>;
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adi,bsync-secondary-frequency-hz = <12500000>; /* 12.5 MHz */
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channel@0 {
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reg = <0>;
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adi,extended-name = "APOLLO_SYSREF_0";
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adi,output-en;
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adi,input-output-reconfig-en;
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auto-align-on-sync-en;
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adi,rcm = <1>;
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adi,link-rx-en;
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adi,float-rx-en;
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};
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channel@1 {
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reg = <1>;
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adi,extended-name = "APOLLO_SYSREF_1";
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adi,output-en;
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adi,input-output-reconfig-en;
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auto-align-on-sync-en;
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adi,rcm = <1>;
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adi,link-rx-en;
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adi,float-rx-en;
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};
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channel@2 {
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reg = <2>;
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adi,extended-name = "APOLLO_SYSREF_2";
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adi,output-en;
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adi,input-output-reconfig-en;
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auto-align-on-sync-en;
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adi,rcm = <1>;
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adi,link-rx-en;
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adi,float-rx-en;
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};
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channel@3 {
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reg = <3>;
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adi,extended-name = "APOLLO_SYSREF_3";
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adi,output-en;
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adi,input-output-reconfig-en;
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auto-align-on-sync-en;
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adi,rcm = <1>;
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adi,link-rx-en;
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adi,float-rx-en;
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};
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channel@4 {
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reg = <4>;
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adi,extended-name = "FPGA_SYSREF_0"; /* RES rotate option for J40/J41 U.FL output */
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adi,output-en;
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adi,input-output-reconfig-en;
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auto-align-on-sync-en;
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adi,rcm = <62>;
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adi,link-rx-en;
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adi,float-rx-en;
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};
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// channel@5 {
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// reg = <5>;
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// adi,extended-name = "FPGA_SYSREF_1"; /* RES rotate option for J42/J43 U.FL output */
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// adi,output-en;
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// adi,input-output-reconfig-en;
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// adi,rcm = <62>;
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// };
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channel@6 {
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reg = <6>;
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adi,extended-name = "LTC6953_OUT_6";
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adi,link-rx-en;
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adi,float-rx-en;
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};
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/* BSYNC7 unused */
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channel@8 {
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reg = <8>;
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adi,extended-name = "LTC6952_OUT_8";
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adi,link-rx-en;
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adi,float-rx-en;
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};
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channel@9 {
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reg = <9>;
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adi,extended-name = "J46_J47_UFL";
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/delete-property/ adi,output-en;
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adi,input-output-reconfig-en;
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auto-align-on-sync-en;
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adi,rcm = <62>;
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};
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};
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};
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&trx0_ad9084 {
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jesd204-stop-states = <
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JESD204_FSM_STATE_OPT_POST_SETUP_STAGE1
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JESD204_FSM_STATE_OPT_POST_SETUP_STAGE2
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JESD204_FSM_STATE_OPT_POST_SETUP_STAGE3>;
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};

‎arch/microblaze/boot/dts/vcu118_quad_ad9084_26p4_revB_ext_second.dts‎

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Analog Devices Quad-AD9084 RevB
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* https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9084
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* https://wiki.analog.com/resources/eval/user-guides/ad9084_fmca_ebz/ad9084_fmca_ebz_hdl
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*
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* hdl_project: <quad_apollo/vcu118>
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* board_revision: <Rev.B>
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*
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* Copyright (C) 2024 Analog Devices Inc.
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*/
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#define DEVICE_PROFILE_NAME "id01_uc43.bin"
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#define MHz 1000000
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#define FREQ_J1_MHz (400 * MHz)
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#define TX_CORE_CLK_MHz (400 * MHz)
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#define RX_CORE_CLK_MHz (400 * MHz)
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#define FPGA_REFCLK_CLK_MHz (400 * MHz)
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#define SYSREF_CLK_MHz (2 * 6250000)
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#include "vcu118_quad_ad9084_revB.dts"
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#include <dt-bindings/jesd204/device-states.h>
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&axi_ethernet {
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local-mac-address = [00 0a 35 02 90 84];
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};
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&axi_spi_2 {
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/delete-node/ adf4030;
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adf4030: adf4030@4 {
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#clock-cells = <1>;
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compatible = "adi,adf4030";
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reg = <4>;
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#address-cells = <1>;
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#size-cells = <0>;
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#io-channel-cells = <1>;
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spi-max-frequency = <1000000>;
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clocks = <&ltc6952 5>;
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clock-names = "refin";
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clock-output-names = "adf4030_bsync_0", "adf4030_bsync_1",
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"adf4030_bsync_2", "adf4030_bsync_3", "adf4030_bsync_4",
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"adf4030_bsync_5", "adf4030_bsync_6", "adf4030_bsync_7",
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"adf4030_bsync_8", "adf4030_bsync_9";
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label = "adf4030";
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jesd204-device;
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#jesd204-cells = <2>;
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jesd204-sysref-provider;
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adi,vco-frequency-hz = <2500000000>; /* 2.5 GHz */
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adi,bsync-frequency-hz = <SYSREF_CLK_MHz>;
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adi,bsync-autoalign-reference-channel = <9>; /* J46_J47_UFL */
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adi,bsync-autoalign-iteration-count = <6>;
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adi,bsync-secondary-frequency-hz = <12500000>; /* 12.5 MHz */
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channel@0 {
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reg = <0>;
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adi,extended-name = "APOLLO_SYSREF_0";
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adi,output-en;
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adi,input-output-reconfig-en;
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auto-align-on-sync-en;
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adi,rcm = <1>;
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adi,link-rx-en;
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adi,float-rx-en;
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};
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channel@1 {
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reg = <1>;
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adi,extended-name = "APOLLO_SYSREF_1";
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adi,output-en;
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adi,input-output-reconfig-en;
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auto-align-on-sync-en;
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adi,rcm = <1>;
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adi,link-rx-en;
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adi,float-rx-en;
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};
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channel@2 {
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reg = <2>;
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adi,extended-name = "APOLLO_SYSREF_2";
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adi,output-en;
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adi,input-output-reconfig-en;
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auto-align-on-sync-en;
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adi,rcm = <1>;
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adi,link-rx-en;
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adi,float-rx-en;
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};
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channel@3 {
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reg = <3>;
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adi,extended-name = "APOLLO_SYSREF_3";
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adi,output-en;
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adi,input-output-reconfig-en;
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auto-align-on-sync-en;
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adi,rcm = <1>;
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adi,link-rx-en;
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adi,float-rx-en;
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};
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channel@4 {
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reg = <4>;
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adi,extended-name = "FPGA_SYSREF_0"; /* RES rotate option for J40/J41 U.FL output */
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adi,output-en;
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adi,input-output-reconfig-en;
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auto-align-on-sync-en;
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adi,rcm = <62>;
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adi,link-rx-en;
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adi,float-rx-en;
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};
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// channel@5 {
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// reg = <5>;
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// adi,extended-name = "FPGA_SYSREF_1"; /* RES rotate option for J42/J43 U.FL output */
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// adi,output-en;
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// adi,input-output-reconfig-en;
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// adi,rcm = <62>;
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// };
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channel@6 {
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reg = <6>;
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adi,extended-name = "LTC6953_OUT_6";
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adi,link-rx-en;
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adi,float-rx-en;
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};
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/* BSYNC7 unused */
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channel@8 {
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reg = <8>;
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adi,extended-name = "LTC6952_OUT_8";
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adi,link-rx-en;
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adi,float-rx-en;
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};
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channel@9 {
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reg = <9>;
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adi,extended-name = "J46_J47_UFL";
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/delete-property/ adi,output-en;
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adi,input-output-reconfig-en;
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auto-align-on-sync-en;
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adi,rcm = <62>;
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};
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};
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};
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&trx0_ad9084 {
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jesd204-stop-states = <
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JESD204_FSM_STATE_OPT_POST_SETUP_STAGE1
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JESD204_FSM_STATE_OPT_POST_SETUP_STAGE2
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JESD204_FSM_STATE_OPT_POST_SETUP_STAGE3>;
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};

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