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sihyung-maximEricB-ADI
sihyung-maxim
authored and
EricB-ADI
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fix(CMSIS,PeriphDrivers): Remove SPI TS3, fix GPIO pad controls, and fix build errors for MAX32657 (#1226)
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11 files changed

+47
-172
lines changed

11 files changed

+47
-172
lines changed

‎Libraries/CMSIS/Device/Maxim/MAX32657/Include/gpio_regs.h‎

Lines changed: 15 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -96,8 +96,8 @@ typedef struct {
9696
__IO uint32_t wken_clr; /**< <tt>\b 0x54:</tt> GPIO WKEN_CLR Register */
9797
__R uint32_t rsv_0x58;
9898
__IO uint32_t dualedge; /**< <tt>\b 0x5C:</tt> GPIO DUALEDGE Register */
99-
__IO uint32_t padctrl0; /**< <tt>\b 0x60:</tt> GPIO PADCTRL0 Register */
100-
__IO uint32_t padctrl1; /**< <tt>\b 0x64:</tt> GPIO PADCTRL1 Register */
99+
__IO uint32_t padctrl; /**< <tt>\b 0x60:</tt> GPIO PADCTRL Register */
100+
__R uint32_t rsv_0x64;
101101
__IO uint32_t en1; /**< <tt>\b 0x68:</tt> GPIO EN1 Register */
102102
__IO uint32_t en1_set; /**< <tt>\b 0x6C:</tt> GPIO EN1_SET Register */
103103
__IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */
@@ -143,8 +143,7 @@ typedef struct {
143143
#define MXC_R_GPIO_WKEN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt> 0x0050</tt> */
144144
#define MXC_R_GPIO_WKEN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt> 0x0054</tt> */
145145
#define MXC_R_GPIO_DUALEDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt> 0x005C</tt> */
146-
#define MXC_R_GPIO_PADCTRL0 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt> 0x0060</tt> */
147-
#define MXC_R_GPIO_PADCTRL1 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt> 0x0064</tt> */
146+
#define MXC_R_GPIO_PADCTRL ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt> 0x0060</tt> */
148147
#define MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt> 0x0068</tt> */
149148
#define MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt> 0x006C</tt> */
150149
#define MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt> 0x0070</tt> */
@@ -473,39 +472,21 @@ typedef struct {
473472

474473
/**
475474
* @ingroup gpio_registers
476-
* @defgroup GPIO_PADCTRL0 GPIO_PADCTRL0
477-
* @brief GPIO Input Mode Config 0. Each bit in this register enables the weak pull-up for
478-
* the associated GPIO pin in this port.
475+
* @defgroup GPIO_PADCTRL GPIO_PADCTRL
476+
* @brief GPIO Pad Control. Each bit in this register configures the pad for the
477+
* associated GPIO pin in this port.
479478
* @{
480479
*/
481-
#define MXC_F_GPIO_PADCTRL0_ALL_POS 0 /**< PADCTRL0_ALL Position */
482-
#define MXC_F_GPIO_PADCTRL0_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL0_ALL_POS)) /**< PADCTRL0_ALL Mask */
483-
#define MXC_V_GPIO_PADCTRL0_ALL_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL0_ALL_IMPEDANCE Value */
484-
#define MXC_S_GPIO_PADCTRL0_ALL_IMPEDANCE (MXC_V_GPIO_PADCTRL0_ALL_IMPEDANCE << MXC_F_GPIO_PADCTRL0_ALL_POS) /**< PADCTRL0_ALL_IMPEDANCE Setting */
485-
#define MXC_V_GPIO_PADCTRL0_ALL_PU ((uint32_t)0x1UL) /**< PADCTRL0_ALL_PU Value */
486-
#define MXC_S_GPIO_PADCTRL0_ALL_PU (MXC_V_GPIO_PADCTRL0_ALL_PU << MXC_F_GPIO_PADCTRL0_ALL_POS) /**< PADCTRL0_ALL_PU Setting */
487-
#define MXC_V_GPIO_PADCTRL0_ALL_PD ((uint32_t)0x2UL) /**< PADCTRL0_ALL_PD Value */
488-
#define MXC_S_GPIO_PADCTRL0_ALL_PD (MXC_V_GPIO_PADCTRL0_ALL_PD << MXC_F_GPIO_PADCTRL0_ALL_POS) /**< PADCTRL0_ALL_PD Setting */
480+
#define MXC_F_GPIO_PADCTRL_ALL_POS 0 /**< PADCTRL_ALL Position */
481+
#define MXC_F_GPIO_PADCTRL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL_ALL_POS)) /**< PADCTRL_ALL Mask */
482+
#define MXC_V_GPIO_PADCTRL_ALL_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL_ALL_IMPEDANCE Value */
483+
#define MXC_S_GPIO_PADCTRL_ALL_IMPEDANCE (MXC_V_GPIO_PADCTRL_ALL_IMPEDANCE << MXC_F_GPIO_PADCTRL_ALL_POS) /**< PADCTRL_ALL_IMPEDANCE Setting */
484+
#define MXC_V_GPIO_PADCTRL_ALL_PU ((uint32_t)0x1UL) /**< PADCTRL_ALL_PU Value */
485+
#define MXC_S_GPIO_PADCTRL_ALL_PU (MXC_V_GPIO_PADCTRL_ALL_PU << MXC_F_GPIO_PADCTRL_ALL_POS) /**< PADCTRL_ALL_PU Setting */
486+
#define MXC_V_GPIO_PADCTRL_ALL_PD ((uint32_t)0x2UL) /**< PADCTRL_ALL_PD Value */
487+
#define MXC_S_GPIO_PADCTRL_ALL_PD (MXC_V_GPIO_PADCTRL_ALL_PD << MXC_F_GPIO_PADCTRL_ALL_POS) /**< PADCTRL_ALL_PD Setting */
489488

490-
/**@} end of group GPIO_PADCTRL0_Register */
491-
492-
/**
493-
* @ingroup gpio_registers
494-
* @defgroup GPIO_PADCTRL1 GPIO_PADCTRL1
495-
* @brief GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for
496-
* the associated GPIO pin in this port.
497-
* @{
498-
*/
499-
#define MXC_F_GPIO_PADCTRL1_ALL_POS 0 /**< PADCTRL1_ALL Position */
500-
#define MXC_F_GPIO_PADCTRL1_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL1_ALL_POS)) /**< PADCTRL1_ALL Mask */
501-
#define MXC_V_GPIO_PADCTRL1_ALL_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL1_ALL_IMPEDANCE Value */
502-
#define MXC_S_GPIO_PADCTRL1_ALL_IMPEDANCE (MXC_V_GPIO_PADCTRL1_ALL_IMPEDANCE << MXC_F_GPIO_PADCTRL1_ALL_POS) /**< PADCTRL1_ALL_IMPEDANCE Setting */
503-
#define MXC_V_GPIO_PADCTRL1_ALL_PU ((uint32_t)0x1UL) /**< PADCTRL1_ALL_PU Value */
504-
#define MXC_S_GPIO_PADCTRL1_ALL_PU (MXC_V_GPIO_PADCTRL1_ALL_PU << MXC_F_GPIO_PADCTRL1_ALL_POS) /**< PADCTRL1_ALL_PU Setting */
505-
#define MXC_V_GPIO_PADCTRL1_ALL_PD ((uint32_t)0x2UL) /**< PADCTRL1_ALL_PD Value */
506-
#define MXC_S_GPIO_PADCTRL1_ALL_PD (MXC_V_GPIO_PADCTRL1_ALL_PD << MXC_F_GPIO_PADCTRL1_ALL_POS) /**< PADCTRL1_ALL_PD Setting */
507-
508-
/**@} end of group GPIO_PADCTRL1_Register */
489+
/**@} end of group GPIO_PADCTRL_Register */
509490

510491
/**
511492
* @ingroup gpio_registers

‎Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd‎

Lines changed: 4 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -3353,8 +3353,8 @@
33533353
</fields>
33543354
</register>
33553355
<register>
3356-
<name>PADCTRL0</name>
3357-
<description>GPIO Input Mode Config 0. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.</description>
3356+
<name>PADCTRL</name>
3357+
<description>GPIO Pad Control. Each bit in this register configures the pad for the associated GPIO pin in this port.</description>
33583358
<addressOffset>0x60</addressOffset>
33593359
<fields>
33603360
<field>
@@ -3382,36 +3382,6 @@
33823382
</field>
33833383
</fields>
33843384
</register>
3385-
<register>
3386-
<name>PADCTRL1</name>
3387-
<description>GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.</description>
3388-
<addressOffset>0x64</addressOffset>
3389-
<fields>
3390-
<field>
3391-
<name>ALL</name>
3392-
<description>The two bits in GPIO_PADCTRL0 and GPIO_PADCTRL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.</description>
3393-
<bitOffset>0</bitOffset>
3394-
<bitWidth>32</bitWidth>
3395-
<enumeratedValues>
3396-
<enumeratedValue>
3397-
<name>impedance</name>
3398-
<description>High Impedance.</description>
3399-
<value>0</value>
3400-
</enumeratedValue>
3401-
<enumeratedValue>
3402-
<name>pu</name>
3403-
<description>Weak pull-up mode.</description>
3404-
<value>1</value>
3405-
</enumeratedValue>
3406-
<enumeratedValue>
3407-
<name>pd</name>
3408-
<description>weak pull-down mode.</description>
3409-
<value>2</value>
3410-
</enumeratedValue>
3411-
</enumeratedValues>
3412-
</field>
3413-
</fields>
3414-
</register>
34153385
<register>
34163386
<name>EN1</name>
34173387
<description>GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.</description>
@@ -8460,11 +8430,6 @@
84608430
<description>TS2 is selected.</description>
84618431
<value>0x4</value>
84628432
</enumeratedValue>
8463-
<enumeratedValue>
8464-
<name>TS3</name>
8465-
<description>TS3 is selected.</description>
8466-
<value>0x8</value>
8467-
</enumeratedValue>
84688433
</enumeratedValues>
84698434
</field>
84708435
</fields>
@@ -8682,7 +8647,7 @@
86828647
<name>TSPOL</name>
86838648
<description>Target Select Polarity, each Target Select can have unique polarity.</description>
86848649
<bitOffset>16</bitOffset>
8685-
<bitWidth>4</bitWidth>
8650+
<bitWidth>3</bitWidth>
86868651
<enumeratedValues>
86878652
<enumeratedValue>
86888653
<name>TS0_high</name>
@@ -8699,11 +8664,6 @@
86998664
<description>TS2 active high.</description>
87008665
<value>0x4</value>
87018666
</enumeratedValue>
8702-
<enumeratedValue>
8703-
<name>TS3_high</name>
8704-
<description>TS3 active high.</description>
8705-
<value>0x8</value>
8706-
</enumeratedValue>
87078667
</enumeratedValues>
87088668
</field>
87098669
</fields>
@@ -10241,9 +10201,8 @@
1024110201
<registers>
1024210202
<register>
1024310203
<name>RTCX1</name>
10244-
<description>RTC X2 Capacitor Setting.</description>
10204+
<description>RTC X1 Capacitor Setting.</description>
1024510205
<addressOffset>0x3C</addressOffset>
10246-
<access>read-only</access>
1024710206
<fields>
1024810207
<field>
1024910208
<name>CAP</name>

‎Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h‎

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -176,8 +176,6 @@ typedef struct {
176176
#define MXC_S_SPI_CTRL0_TS_ACTIVE_TS1 (MXC_V_SPI_CTRL0_TS_ACTIVE_TS1 << MXC_F_SPI_CTRL0_TS_ACTIVE_POS) /**< CTRL0_TS_ACTIVE_TS1 Setting */
177177
#define MXC_V_SPI_CTRL0_TS_ACTIVE_TS2 ((uint32_t)0x4UL) /**< CTRL0_TS_ACTIVE_TS2 Value */
178178
#define MXC_S_SPI_CTRL0_TS_ACTIVE_TS2 (MXC_V_SPI_CTRL0_TS_ACTIVE_TS2 << MXC_F_SPI_CTRL0_TS_ACTIVE_POS) /**< CTRL0_TS_ACTIVE_TS2 Setting */
179-
#define MXC_V_SPI_CTRL0_TS_ACTIVE_TS3 ((uint32_t)0x8UL) /**< CTRL0_TS_ACTIVE_TS3 Value */
180-
#define MXC_S_SPI_CTRL0_TS_ACTIVE_TS3 (MXC_V_SPI_CTRL0_TS_ACTIVE_TS3 << MXC_F_SPI_CTRL0_TS_ACTIVE_POS) /**< CTRL0_TS_ACTIVE_TS3 Setting */
181179

182180
/**@} end of group SPI_CTRL0_Register */
183181

@@ -258,15 +256,13 @@ typedef struct {
258256
#define MXC_F_SPI_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */
259257

260258
#define MXC_F_SPI_CTRL2_TSPOL_POS 16 /**< CTRL2_TSPOL Position */
261-
#define MXC_F_SPI_CTRL2_TSPOL ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_TSPOL_POS)) /**< CTRL2_TSPOL Mask */
259+
#define MXC_F_SPI_CTRL2_TSPOL ((uint32_t)(0x7UL << MXC_F_SPI_CTRL2_TSPOL_POS)) /**< CTRL2_TSPOL Mask */
262260
#define MXC_V_SPI_CTRL2_TSPOL_TS0_HIGH ((uint32_t)0x1UL) /**< CTRL2_TSPOL_TS0_HIGH Value */
263261
#define MXC_S_SPI_CTRL2_TSPOL_TS0_HIGH (MXC_V_SPI_CTRL2_TSPOL_TS0_HIGH << MXC_F_SPI_CTRL2_TSPOL_POS) /**< CTRL2_TSPOL_TS0_HIGH Setting */
264262
#define MXC_V_SPI_CTRL2_TSPOL_TS1_HIGH ((uint32_t)0x2UL) /**< CTRL2_TSPOL_TS1_HIGH Value */
265263
#define MXC_S_SPI_CTRL2_TSPOL_TS1_HIGH (MXC_V_SPI_CTRL2_TSPOL_TS1_HIGH << MXC_F_SPI_CTRL2_TSPOL_POS) /**< CTRL2_TSPOL_TS1_HIGH Setting */
266264
#define MXC_V_SPI_CTRL2_TSPOL_TS2_HIGH ((uint32_t)0x4UL) /**< CTRL2_TSPOL_TS2_HIGH Value */
267265
#define MXC_S_SPI_CTRL2_TSPOL_TS2_HIGH (MXC_V_SPI_CTRL2_TSPOL_TS2_HIGH << MXC_F_SPI_CTRL2_TSPOL_POS) /**< CTRL2_TSPOL_TS2_HIGH Setting */
268-
#define MXC_V_SPI_CTRL2_TSPOL_TS3_HIGH ((uint32_t)0x8UL) /**< CTRL2_TSPOL_TS3_HIGH Value */
269-
#define MXC_S_SPI_CTRL2_TSPOL_TS3_HIGH (MXC_V_SPI_CTRL2_TSPOL_TS3_HIGH << MXC_F_SPI_CTRL2_TSPOL_POS) /**< CTRL2_TSPOL_TS3_HIGH Setting */
270266

271267
/**@} end of group SPI_CTRL2_Register */
272268

‎Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,7 @@ extern "C" {
7373
*/
7474
typedef struct {
7575
__R uint32_t rsv_0x0_0x3b[15];
76-
__I uint32_t rtcx1; /**< <tt>\b 0x3C:</tt> TRIMSIR RTCX1 Register */
76+
__IO uint32_t rtcx1; /**< <tt>\b 0x3C:</tt> TRIMSIR RTCX1 Register */
7777
__R uint32_t rsv_0x40;
7878
__IO uint32_t rtcx2; /**< <tt>\b 0x44:</tt> TRIMSIR RTCX2 Register */
7979
} mxc_trimsir_regs_t;
@@ -92,7 +92,7 @@ typedef struct {
9292
/**
9393
* @ingroup trimsir_registers
9494
* @defgroup TRIMSIR_RTCX1 TRIMSIR_RTCX1
95-
* @brief RTC X2 Capacitor Setting.
95+
* @brief RTC X1 Capacitor Setting.
9696
* @{
9797
*/
9898
#define MXC_F_TRIMSIR_RTCX1_CAP_POS 0 /**< RTCX1_CAP Position */

‎Libraries/PeriphDrivers/Include/MAX32657/gpio.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -151,8 +151,6 @@ typedef enum {
151151
*/
152152
typedef enum {
153153
MXC_GPIO_PAD_NONE, /**< No pull-up or pull-down */
154-
MXC_GPIO_PAD_PULL_UP, /**< Set pad to strong pull-up */
155-
MXC_GPIO_PAD_PULL_DOWN, /**< Set pad to strong pull-down */
156154
MXC_GPIO_PAD_WEAK_PULL_UP, /**< Set pad to weak pull-up */
157155
MXC_GPIO_PAD_WEAK_PULL_DOWN /**< Set pad to weak pull-down */
158156
} mxc_gpio_pad_t;

‎Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c‎

Lines changed: 3 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -96,33 +96,16 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg)
9696
// Configure the pad
9797
switch (cfg->pad) {
9898
case MXC_GPIO_PAD_NONE:
99-
gpio->padctrl0 &= ~cfg->mask;
100-
gpio->padctrl1 &= ~cfg->mask;
99+
gpio->padctrl &= ~cfg->mask;
101100
break;
102101

103-
// Note: for "ps" field set 1 for weak and 0 for strong.
104-
// As of 8-28-2024 most UG tables have this flipped the wrong way
105102
case MXC_GPIO_PAD_WEAK_PULL_UP:
106-
gpio->padctrl0 |= cfg->mask;
107-
gpio->padctrl1 &= ~cfg->mask;
103+
gpio->padctrl |= cfg->mask;
108104
gpio->pssel |= cfg->mask;
109105
break;
110106

111-
case MXC_GPIO_PAD_PULL_UP:
112-
gpio->padctrl0 |= cfg->mask;
113-
gpio->padctrl1 &= ~cfg->mask;
114-
gpio->pssel &= ~cfg->mask;
115-
break;
116-
117107
case MXC_GPIO_PAD_WEAK_PULL_DOWN:
118-
gpio->padctrl0 &= ~cfg->mask;
119-
gpio->padctrl1 |= cfg->mask;
120-
gpio->pssel |= cfg->mask;
121-
break;
122-
123-
case MXC_GPIO_PAD_PULL_DOWN:
124-
gpio->padctrl0 &= ~cfg->mask;
125-
gpio->padctrl1 |= cfg->mask;
108+
gpio->padctrl |= cfg->mask;
126109
gpio->pssel &= ~cfg->mask;
127110
break;
128111

‎Libraries/PeriphDrivers/Source/GPIO/gpio_reva_me30.svd‎

Lines changed: 2 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -443,8 +443,8 @@
443443
</fields>
444444
</register>
445445
<register>
446-
<name>PADCTRL0</name>
447-
<description>GPIO Input Mode Config 0. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.</description>
446+
<name>PADCTRL</name>
447+
<description>GPIO Pad Control. Each bit in this register configures the pad for the associated GPIO pin in this port.</description>
448448
<addressOffset>0x60</addressOffset>
449449
<fields>
450450
<field>
@@ -472,36 +472,6 @@
472472
</field>
473473
</fields>
474474
</register>
475-
<register>
476-
<name>PADCTRL1</name>
477-
<description>GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.</description>
478-
<addressOffset>0x64</addressOffset>
479-
<fields>
480-
<field>
481-
<name>ALL</name>
482-
<description>The two bits in GPIO_PADCTRL0 and GPIO_PADCTRL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.</description>
483-
<bitOffset>0</bitOffset>
484-
<bitWidth>32</bitWidth>
485-
<enumeratedValues>
486-
<enumeratedValue>
487-
<name>impedance</name>
488-
<description>High Impedance.</description>
489-
<value>0</value>
490-
</enumeratedValue>
491-
<enumeratedValue>
492-
<name>pu</name>
493-
<description>Weak pull-up mode.</description>
494-
<value>1</value>
495-
</enumeratedValue>
496-
<enumeratedValue>
497-
<name>pd</name>
498-
<description>weak pull-down mode.</description>
499-
<value>2</value>
500-
</enumeratedValue>
501-
</enumeratedValues>
502-
</field>
503-
</fields>
504-
</register>
505475
<register>
506476
<name>EN1</name>
507477
<description>GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.</description>

‎Libraries/PeriphDrivers/Source/RTC/rtc_me30.c‎

Lines changed: 10 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -151,13 +151,10 @@ int MXC_RTC_GetBusyFlag(void)
151151
return MXC_RTC_RevA_GetBusyFlag((mxc_rtc_reva_regs_t *)MXC_RTC);
152152
}
153153

154+
// TODO(SW): TRIMSIR RTC X1/X2 register descriptions were updated due to design changes.
155+
// CAP vs TRIM value differences unknown, and this function has not been tested.
154156
int MXC_RTC_TrimCrystal(void)
155157
{
156-
#if TARGET_NUM == 78000
157-
/* MAX78000 does not have the ERFO clock which the Trim function requires */
158-
return E_NOT_SUPPORTED;
159-
#endif
160-
161158
unsigned int search_step, elapsed;
162159
unsigned int upper, lower, trim, oldtrim, bestTrim, bestElapsed, bestElapsedDiff;
163160
unsigned int freq = NOM_32K_FREQ;
@@ -209,10 +206,10 @@ int MXC_RTC_TrimCrystal(void)
209206
}
210207

211208
/* Set the trim values */
212-
MXC_SETFIELD(MXC_TRIMSIR->rtc, MXC_F_TRIMSIR_RTC_X1TRIM,
213-
(trim << MXC_F_TRIMSIR_RTC_X1TRIM_POS));
214-
MXC_SETFIELD(MXC_TRIMSIR->rtc, MXC_F_TRIMSIR_RTC_X2TRIM,
215-
(trim << MXC_F_TRIMSIR_RTC_X2TRIM_POS));
209+
MXC_SETFIELD(MXC_TRIMSIR->rtcx1, MXC_F_TRIMSIR_RTCX1_CAP,
210+
(trim << MXC_F_TRIMSIR_RTCX1_CAP_POS));
211+
MXC_SETFIELD(MXC_TRIMSIR->rtcx2, MXC_F_TRIMSIR_RTCX2_CAP,
212+
(trim << MXC_F_TRIMSIR_RTCX2_CAP_POS));
216213

217214
/* Sleep to settle new caps */
218215
MXC_Delay(MXC_DELAY_MSEC(10));
@@ -263,10 +260,10 @@ int MXC_RTC_TrimCrystal(void)
263260
}
264261

265262
/* Apply the closest trim setting */
266-
MXC_SETFIELD(MXC_TRIMSIR->rtc, MXC_F_TRIMSIR_RTC_X1TRIM,
267-
(bestTrim << MXC_F_TRIMSIR_RTC_X1TRIM_POS));
268-
MXC_SETFIELD(MXC_TRIMSIR->rtc, MXC_F_TRIMSIR_RTC_X2TRIM,
269-
(bestTrim << MXC_F_TRIMSIR_RTC_X2TRIM_POS));
263+
MXC_SETFIELD(MXC_TRIMSIR->rtcx1, MXC_F_TRIMSIR_RTCX1_CAP,
264+
(bestTrim << MXC_F_TRIMSIR_RTCX1_CAP_POS));
265+
MXC_SETFIELD(MXC_TRIMSIR->rtcx2, MXC_F_TRIMSIR_RTCX2_CAP,
266+
(bestTrim << MXC_F_TRIMSIR_RTCX2_CAP_POS));
270267

271268
/* Adjust 32K freq if we can't get close enough to 32768 Hz */
272269
if (bestElapsed >= SEARCH_TARGET) {

‎Libraries/PeriphDrivers/Source/SPI/spi_reva_me30.svd‎

Lines changed: 1 addition & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -177,11 +177,6 @@
177177
<description>TS2 is selected.</description>
178178
<value>0x4</value>
179179
</enumeratedValue>
180-
<enumeratedValue>
181-
<name>TS3</name>
182-
<description>TS3 is selected.</description>
183-
<value>0x8</value>
184-
</enumeratedValue>
185180
</enumeratedValues>
186181
</field>
187182
</fields>
@@ -399,7 +394,7 @@
399394
<name>TSPOL</name>
400395
<description>Target Select Polarity, each Target Select can have unique polarity.</description>
401396
<bitOffset>16</bitOffset>
402-
<bitWidth>4</bitWidth>
397+
<bitWidth>3</bitWidth>
403398
<enumeratedValues>
404399
<enumeratedValue>
405400
<name>TS0_high</name>
@@ -416,11 +411,6 @@
416411
<description>TS2 active high.</description>
417412
<value>0x4</value>
418413
</enumeratedValue>
419-
<enumeratedValue>
420-
<name>TS3_high</name>
421-
<description>TS3 active high.</description>
422-
<value>0x8</value>
423-
</enumeratedValue>
424414
</enumeratedValues>
425415
</field>
426416
</fields>

‎Libraries/PeriphDrivers/Source/SYS/SVD/trimsir_me30.svd‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,9 +12,8 @@
1212
<registers>
1313
<register>
1414
<name>RTCX1</name>
15-
<description>RTC X2 Capacitor Setting.</description>
15+
<description>RTC X1 Capacitor Setting.</description>
1616
<addressOffset>0x3C</addressOffset>
17-
<access>read-only</access>
1817
<fields>
1918
<field>
2019
<name>CAP</name>

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