adi: admfm8000: initial helper class for FMCW TX board

Signed-off-by: Rodrigo Alencar <rodrigo.alencar@analog.com>

Author: rodrigo455

adi/__init__.py

@@ -90,6 +90,7 @@
 from adi.adis16550 import adis16550
 from adi.adl5240 import adl5240
 from adi.adl5960 import adl5960
+from adi.admfm8000 import admfm8000
 from adi.admv8818 import admv8818
 from adi.adpd188 import adpd188
 from adi.adpd410x import adpd410x

adi/admfm8000.py

@@ -0,0 +1,232 @@
+# Copyright (C) 2026 Analog Devices, Inc.
+#
+# SPDX short identifier: ADIBSD
+
+import warnings
+
+from adi.ad9910 import ad9910
+from adi.adf41513 import adf41513
+from adi.adrf5720 import adrf5720
+
+
+class admfm8000:
+    """ADMFM8000 FMCW Transmitter
+
+    This class provides a high-level interface for controlling the ADMFM8000.
+    The system consists of an AD9910 DDS, an ADF41513 PLL, and an ADRF5720 DSA.
+    Helper functions to configure the DDS modes have the frequency values
+    automatically scaled down based on the PLL reference input frequency and the
+    desired VCO output frequency.
+    """
+
+    def __init__(self, uri="", vco_feedback_div=16, pll_refin_frequency=50e6):
+        self.dds = ad9910(uri)
+        self.pll = adf41513(uri)
+        self.dsa = adrf5720(uri, "adrf5730")
+        self._pll_refin_init_frequency = pll_refin_frequency
+        self._pll_refin_frequency = pll_refin_frequency
+        self._vco_feedback_div = vco_feedback_div
+        self.vco_frequency = 25.6e9
+
+    @property
+    def attenuation(self):
+        """Get/Set the DSA attenuation in dB"""
+        return self.dsa.attenuation
+
+    @attenuation.setter
+    def attenuation(self, value):
+        self.dsa.attenuation = value
+
+    @property
+    def pll_refin_frequency(self):
+        """Get/Set the PLL reference input frequency in Hz
+
+        This value should represent the center frequency of the signal generated
+        by the DDS that is fed into the PLL reference input.
+        """
+        return self._pll_refin_frequency
+
+    @pll_refin_frequency.setter
+    def pll_refin_frequency(self, value):
+        if value > 80e6 or value < 10e6:
+            raise ValueError("Invalid PLL RefIn frequency")
+        self._pll_refin_frequency = value
+        self.vco_frequency = self._vco_frequency
+
+    @property
+    def vco_frequency(self):
+        """Get/Set the VCO frequency output value in Hz
+
+        This value should represent the center frequency of the signal generated
+        by the external VCO. It takes into account the current PLL settings and
+        the VCO feedback divider.
+        """
+        return self._vco_frequency
+
+    @vco_frequency.setter
+    def vco_frequency(self, value):
+        pll_multiplier = (value / self._vco_feedback_div) / self._pll_refin_frequency
+        self.pll.frequency = pll_multiplier * self._pll_refin_init_frequency
+        self._vco_frequency = value
+
+    @property
+    def frequency_scaling_factor(self):
+        """Get the overall frequency scaling factor based on current PLL and VCO
+        settings
+
+        This value takes into account the PLL settings and the feedback divider
+        to calculate the effective frequency scaling factor.
+        """
+        return self._vco_frequency / self._pll_refin_frequency
+
+    def single_tone_config(self, profile=0, frequency=None, scale=None, phase=None):
+        """Configure the DDS for single tone output with respect to VCO frequency output.
+
+        :param profile: DDS Profile number
+        :param frequency: Output frequency in Hz
+        :param scale: Output scale (0.0 to 1.0)
+        :param phase: Output phase in radians
+        """
+        self.dds.profile = profile
+        if frequency is not None:
+            self.dds.st.profiles[profile].frequency = (
+                frequency / self.frequency_scaling_factor
+            )
+        if phase is not None:
+            self.dds.st.profiles[profile].phase = phase
+        if scale is not None:
+            self.dds.st.profiles[profile].scale = scale
+
+    def parallel_port_config(
+        self, enable=True, frequency_np=None, cyclic=True, rate=None
+    ):
+        """Configure the DDS Parallel Port channel
+
+        :param enable: Enable/Disable the Parallel Port channel
+        :param frequency_np: numpy array of frequency values in Hz
+        :param cyclic: Enable/Disable cyclic mode for the DMA buffer
+        :param rate: Rate of the Parallel Port channel in samples/second
+        """
+        if enable:
+            self.dds.parallel_port.enable = 1
+        else:
+            self.dds.tx_destroy_buffer()
+            self.dds.parallel_port.enable = 0
+
+        if rate is not None:
+            try:
+                self.dds.parallel_port.rate = rate
+            except Exception as ex:
+                warnings.warn(f"Failed to set Parallel Port rate: {ex}")
+
+        if frequency_np is not None:
+            self.dds.parallel_port.frequency_push(
+                frequency_np / self.frequency_scaling_factor, cyclic=cyclic
+            )
+
+    def digital_ramp_config(
+        self,
+        enable=None,
+        mode=None,
+        freq_min=None,
+        freq_max=None,
+        inc_step=None,
+        dec_step=None,
+        inc_rate=None,
+        dec_rate=None,
+        inc_ramp_time=None,
+        dec_ramp_time=None,
+        **kwargs,
+    ):
+        """Configure the DDS Digital Ramp Generator (DRG)
+
+        :param enable: Enable/Disable the Digital Ramp Generator
+        :param mode: DRG Operating Mode as defined in ad9910.digital_ramp_generator.mode
+        :param freq_min: Minimum frequency in Hz
+        :param freq_max: Maximum frequency in Hz
+        :param inc_step: Increment step in Hz
+        :param dec_step: Decrement step in Hz
+        :param inc_rate: Increment rate in samples/second
+        :param dec_rate: Decrement rate in samples/second
+        :param inc_ramp_time: Ramp time for increment in seconds
+        :param dec_ramp_time: Ramp time for decrement in seconds
+        :param kwargs: Additional DRG attributes to set as key-value pairs
+        """
+        if enable:
+            # disable DRG when updating settings.
+            # This ensures that HDL starts from a known state.
+            self.dds.drg.enable = 0
+
+        self.dds.drg.destination = ad9910.destination.FREQUENCY
+
+        for attr, value in kwargs.items():
+            try:
+                self.dds.drg._set_iio_attr(attr, value)
+            except Exception as ex:
+                warnings.warn(f"Failed to set attribute {attr} on DRG channel: {ex}")
+
+        if freq_min is not None:
+            self.dds.drg.frequency.min = freq_min / self.frequency_scaling_factor
+        else:
+            freq_min = self.dds.drg.frequency.min * self.frequency_scaling_factor
+
+        if freq_max is not None:
+            self.dds.drg.frequency.max = freq_max / self.frequency_scaling_factor
+        else:
+            freq_max = self.dds.drg.frequency.max * self.frequency_scaling_factor
+
+        if mode is not None:
+            self.dds.drg.operating_mode = mode
+
+        if inc_step is None and inc_rate is None and inc_ramp_time is not None:
+            inc_rate = self.dds.sysclk_frequency / 4  # max DRG update rate
+            inc_step = (freq_max - freq_min) / (inc_rate * inc_ramp_time)
+
+        if dec_step is None and dec_rate is None and dec_ramp_time is not None:
+            dec_rate = self.dds.sysclk_frequency / 4  # max DRG update rate
+            dec_step = (freq_max - freq_min) / (dec_rate * dec_ramp_time)
+
+        if inc_step is not None:
+            self.dds.drg.frequency.increment = inc_step / self.frequency_scaling_factor
+        if dec_step is not None:
+            self.dds.drg.frequency.decrement = dec_step / self.frequency_scaling_factor
+        if inc_rate is not None:
+            self.dds.drg.increment_rate = inc_rate
+        if dec_rate is not None:
+            self.dds.drg.decrement_rate = dec_rate
+        if enable is not None:
+            self.dds.drg.enable = 1 if enable else 0
+
+    def ram_control_profile_config(
+        self, profile=0, mode=None, addr_range=None, rate=None
+    ):
+        """Configure the DDS RAM Control Profiles
+
+        :param profile: RAM Control Profile number
+        :param mode: RAM Control Mode as defined in ad9910.ram_control.mode
+        :param addr_range: RAM address range as a tuple (start_addr, end_addr)
+        :param rate: RAM update rate in samples/second
+        """
+        self.dds.profile = profile
+        if isinstance(addr_range, tuple) and len(addr_range) == 2:
+            self.dds.ram.profiles[profile].address_range = addr_range
+        if mode is not None:
+            self.dds.ram.profiles[profile].operating_mode = mode
+        if rate is not None:
+            self.dds.ram.profiles[profile].rate = rate
+
+    def ram_control_config(self, enable=True, frequency_np=None):
+        """Load frequency list with respect to VCO frequency output into DDS RAM in Hz
+
+        :param enable: Enable/Disable the RAM Mode
+        :param frequency_np: numpy array of frequency values in Hz
+        """
+        if frequency_np is not None:
+            if self.dds.ram.enable == 1:
+                # make sure RAM is disabled before loading new values
+                self.dds.ram.enable = 0
+
+            self.dds.ram.destination = ad9910.destination.FREQUENCY
+            self.dds.ram.frequency_load(frequency_np / self.frequency_scaling_factor)
+
+        self.dds.ram.enable = 1 if enable else 0

doc/source/devices/adi.admfm8000.rst

@@ -0,0 +1,7 @@
+adi.admfm8000 module
+====================
+
+.. automodule:: adi.admfm8000
+   :members:
+   :undoc-members:
+   :show-inheritance:

doc/source/devices/index.rst

@@ -96,6 +96,7 @@ Supported Devices
    adi.adis16550
    adi.adl5240
    adi.adl5960
+   adi.admfm8000
    adi.admv8818
    adi.adpd1080
    adi.adpd188