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mtl_rwc_ratios.py
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7106 lines (6318 loc) · 267 KB
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# -*- coding: latin-1 -*-
#
# auto generated TopDown/TMA 5.1-full description for Intel 14th gen Core (code name Meteor Lake) with Redwood Cove
# Please see http://ark.intel.com for more details on these CPUs.
#
# References:
# http://bit.ly/tma-ispass14
# http://halobates.de/blog/p/262
# https://sites.google.com/site/analysismethods/yasin-pubs
# https://github.com/intel/perfmon
# https://github.com/andikleen/pmu-tools/wiki/toplev-manual
#
# Helpers
print_error = lambda msg: False
ebs_mode = False
version = "5.1-full"
base_frequency = -1.0
Memory = 0
Average_Frequency = 0.0
num_cores = 1
num_threads = 1
num_sockets = 1
smt_enabled = False
topdown_use_fixed = False
def handle_error(obj, msg):
print_error(msg)
obj.errcount += 1
obj.val = 0
obj.thresh = False
def handle_error_metric(obj, msg):
print_error(msg)
obj.errcount += 1
obj.val = 0
# Constants
Exe_Ports = 12
Mem_L2_Store_Cost = 10
Mem_STLB_Hit_Cost = 7
MS_Switches_Cost = 3
Avg_Assist_Cost = ( 99 *3 + 63 + 30 ) / 5
Pipeline_Width = 6
DSB_Width = 8
MITE_Width = 6
Decode_Width = 6
MS_Width = 4
Retire_Width = 8
OneMillion = 1000000
OneBillion = 1000000000
Energy_Unit = 61
PERF_METRICS_MSR = 1
DS = 0
# Aux. formulas
def Br_DoI_Jumps(self, EV, level):
return EV("BR_INST_RETIRED.NEAR_TAKEN", level) - EV("BR_INST_RETIRED.COND_TAKEN", level) - 2 * EV("BR_INST_RETIRED.NEAR_CALL", level)
def Branching_Retired(self, EV, level):
return (EV("BR_INST_RETIRED.ALL_BRANCHES", level) + 2 * EV("BR_INST_RETIRED.NEAR_CALL", level) + EV("INST_RETIRED.NOP", level)) / SLOTS(self, EV, level)
def Serialize_Core(self, EV, level):
return self.Core_Bound.compute(EV) * (self.Serializing_Operation.compute(EV) + EV("RS.EMPTY_RESOURCE", level) / CLKS(self, EV, level) * self.Ports_Utilized_0.compute(EV)) / (self.Divider.compute(EV) + self.Ports_Utilization.compute(EV) + self.Serializing_Operation.compute(EV))
def Umisp(self, EV, level):
return 10 * self.Microcode_Sequencer.compute(EV) * self.Other_Mispredicts.compute(EV) / self.Branch_Mispredicts.compute(EV)
def Assist(self, EV, level):
return (self.Microcode_Sequencer.compute(EV) / (self.Few_Uops_Instructions.compute(EV) + self.Microcode_Sequencer.compute(EV))) * (self.Assists.compute(EV) / self.Microcode_Sequencer.compute(EV))
def Assist_Frontend(self, EV, level):
return (1 - EV("INST_RETIRED.REP_ITERATION", level) / EV("UOPS_RETIRED.MS:c1", level)) * (self.Fetch_Latency.compute(EV) * (self.MS_Switches.compute(EV) + self.Branch_Resteers.compute(EV) * (self.Clears_Resteers.compute(EV) + self.Mispredicts_Resteers.compute(EV) * self.Other_Mispredicts.compute(EV) / self.Branch_Mispredicts.compute(EV)) / (self.Mispredicts_Resteers.compute(EV) + self.Unknown_Branches.compute(EV) + self.Clears_Resteers.compute(EV))) / (self.Branch_Resteers.compute(EV) + self.MS_Switches.compute(EV) + self.ICache_Misses.compute(EV) + self.LCP.compute(EV) + self.ITLB_Misses.compute(EV) + self.DSB_Switches.compute(EV)) + self.MS.compute(EV))
def Assist_Retired(self, EV, level):
return Assist(self, EV, level) * self.Heavy_Operations.compute(EV)
def Core_Bound_Cycles(self, EV, level):
return self.Ports_Utilized_0.compute(EV) * CLKS(self, EV, level) + Few_Uops_Executed_Threshold(self, EV, level)
def DurationTimeInSeconds(self, EV, level):
return EV("interval-ms", 0) / 1000
def Execute_Cycles(self, EV, level):
return (EV("UOPS_EXECUTED.CORE_CYCLES_GE_1", level) / 2) if smt_enabled else EV("UOPS_EXECUTED.THREAD:c1", level)
# factor used for metrics associating fixed costs for FB Hits - according to probability theory if all FB Hits come at a random rate in original L1_Miss cost interval then the average cost for each one is 0.5 of the fixed cost
def FB_Factor(self, EV, level):
return 1 + FBHit_per_L1Miss(self, EV, level) / 2
def FBHit_per_L1Miss(self, EV, level):
return EV("MEM_LOAD_RETIRED.FB_HIT", level) / EV("MEM_LOAD_RETIRED.L1_MISS", level)
def Fetched_Uops(self, EV, level):
return EV("UOPS_ISSUED.ANY", level)
def Few_Uops_Executed_Threshold(self, EV, level):
return EV("EXE_ACTIVITY.1_PORTS_UTIL", level) + self.Retiring.compute(EV) * EV("EXE_ACTIVITY.2_3_PORTS_UTIL", level)
# Floating Point computational (arithmetic) Operations Count
def FLOP_Count(self, EV, level):
return EV("FP_ARITH_INST_RETIRED.SCALAR", level) + 2 * EV("FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", level) + 4 * EV("FP_ARITH_INST_RETIRED.4_FLOPS", level) + 8 * EV("FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", level)
def FP_Arith_Scalar(self, EV, level):
return EV("FP_ARITH_INST_RETIRED.SCALAR", level)
def FP_Arith_Vector(self, EV, level):
return EV("FP_ARITH_INST_RETIRED.VECTOR", level)
def HighIPC(self, EV, level):
val = IPC(self, EV, level) / Pipeline_Width
return val
def Light_Ops_Sum(self, EV, level):
return self.FP_Arith.compute(EV) + self.Int_Operations.compute(EV) + self.Memory_Operations.compute(EV) + self.Fused_Instructions.compute(EV) + self.Non_Fused_Branches.compute(EV)
def MEM_Bound_Ratio(self, EV, level):
return EV("MEMORY_ACTIVITY.STALLS_L3_MISS", level) / CLKS(self, EV, level)
def Mem_Lock_St_Fraction(self, EV, level):
return EV("MEM_INST_RETIRED.LOCK_LOADS", level) / EV("MEM_INST_RETIRED.ALL_STORES", level)
def Mispred_Clears_Fraction(self, EV, level):
return self.Branch_Mispredicts.compute(EV) / self.Bad_Speculation.compute(EV)
def ORO_Demand_RFO_C1(self, EV, level):
return EV(lambda EV , level : min(EV("CPU_CLK_UNHALTED.THREAD", level) , EV("OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", level)) , level )
def ORO_DRD_Any_Cycles(self, EV, level):
return EV(lambda EV , level : min(EV("CPU_CLK_UNHALTED.THREAD", level) , EV("OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", level)) , level )
def ORO_DRD_BW_Cycles(self, EV, level):
return EV(lambda EV , level : min(EV("CPU_CLK_UNHALTED.THREAD", level) , EV("OFFCORE_REQUESTS_OUTSTANDING.DATA_RD:c4", level)) , level )
def Store_L2_Hit_Cycles(self, EV, level):
return EV("MEM_STORE_RETIRED.L2_HIT", level) * Mem_L2_Store_Cost *(1 - Mem_Lock_St_Fraction(self, EV, level))
def True_XSNP_HitM_Fraction(self, EV, level):
return EV("OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", level) / (EV("OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", level) + EV("OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", level))
def Mem_XSNP_HitM_Cost(self, EV, level):
return 28 * Core_Frequency(self, EV, level)
def Mem_XSNP_Hit_Cost(self, EV, level):
return 27 * Core_Frequency(self, EV, level)
def Mem_XSNP_None_Cost(self, EV, level):
return 12 * Core_Frequency(self, EV, level)
def Mem_L2_Hit_Cost(self, EV, level):
return 3 * Core_Frequency(self, EV, level)
def PERF_METRICS_SUM(self, EV, level):
return (EV("PERF_METRICS.FRONTEND_BOUND", level) / EV("TOPDOWN.SLOTS", level)) + (EV("PERF_METRICS.BAD_SPECULATION", level) / EV("TOPDOWN.SLOTS", level)) + (EV("PERF_METRICS.RETIRING", level) / EV("TOPDOWN.SLOTS", level)) + (EV("PERF_METRICS.BACKEND_BOUND", level) / EV("TOPDOWN.SLOTS", level))
def Retire_Fraction(self, EV, level):
return EV("UOPS_RETIRED.SLOTS", level) / EV("UOPS_ISSUED.ANY", level)
def Retired_Slots(self, EV, level):
return self.Retiring.compute(EV) * SLOTS(self, EV, level)
# Number of logical processors (enabled or online) on the target system
def Num_CPUs(self, EV, level):
return num_cores * num_threads if num_cores else(8 + 16 /(2 - smt_enabled))
# A system parameter for dependent-loads (pointer chasing like access pattern) of the workload. An integer fraction in range from 0 (no dependent loads) to 100 (all loads are dependent loads)
def Dependent_Loads_Weight(self, EV, level):
return 20
# Total pipeline cost of Branch Misprediction related bottlenecks
def Mispredictions(self, EV, level):
val = 100 *(1 - Umisp(self, EV, level)) * (self.Branch_Mispredicts.compute(EV) + self.Fetch_Latency.compute(EV) * self.Mispredicts_Resteers.compute(EV) / (self.Branch_Resteers.compute(EV) + self.MS_Switches.compute(EV) + self.ICache_Misses.compute(EV) + self.LCP.compute(EV) + self.ITLB_Misses.compute(EV) + self.DSB_Switches.compute(EV)))
self.thresh = (val > 20)
return val
# Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)
def Big_Code(self, EV, level):
val = 100 * self.Fetch_Latency.compute(EV) * (self.ITLB_Misses.compute(EV) + self.ICache_Misses.compute(EV) + self.Unknown_Branches.compute(EV)) / (self.Branch_Resteers.compute(EV) + self.MS_Switches.compute(EV) + self.ICache_Misses.compute(EV) + self.LCP.compute(EV) + self.ITLB_Misses.compute(EV) + self.DSB_Switches.compute(EV))
self.thresh = (val > 20)
return val
# Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)
def Instruction_Fetch_BW(self, EV, level):
val = 100 *(self.Frontend_Bound.compute(EV) - (1 - Umisp(self, EV, level)) * self.Fetch_Latency.compute(EV) * self.Mispredicts_Resteers.compute(EV) / (self.Branch_Resteers.compute(EV) + self.MS_Switches.compute(EV) + self.ICache_Misses.compute(EV) + self.LCP.compute(EV) + self.ITLB_Misses.compute(EV) + self.DSB_Switches.compute(EV)) - Assist_Frontend(self, EV, level)) - Big_Code(self, EV, level)
self.thresh = (val > 20)
return val
# Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks
def Data_Cache_Memory_Bandwidth(self, EV, level):
val = 100 *((self.Memory_Bound.compute(EV) * (self.DRAM_Bound.compute(EV) / (self.DRAM_Bound.compute(EV) + self.L2_Bound.compute(EV) + self.L3_Bound.compute(EV) + self.Store_Bound.compute(EV) + self.L1_Bound.compute(EV))) * (self.MEM_Bandwidth.compute(EV) / (self.MEM_Bandwidth.compute(EV) + self.MEM_Latency.compute(EV)))) + (self.Memory_Bound.compute(EV) * (self.L3_Bound.compute(EV) / (self.DRAM_Bound.compute(EV) + self.L2_Bound.compute(EV) + self.L3_Bound.compute(EV) + self.Store_Bound.compute(EV) + self.L1_Bound.compute(EV))) * (self.SQ_Full.compute(EV) / (self.Data_Sharing.compute(EV) + self.Contested_Accesses.compute(EV) + self.L3_Hit_Latency.compute(EV) + self.SQ_Full.compute(EV)))) + (self.Memory_Bound.compute(EV) * (self.L1_Bound.compute(EV) / (self.DRAM_Bound.compute(EV) + self.L2_Bound.compute(EV) + self.L3_Bound.compute(EV) + self.Store_Bound.compute(EV) + self.L1_Bound.compute(EV))) * (self.FB_Full.compute(EV) / (self.DTLB_Load.compute(EV) + self.Lock_Latency.compute(EV) + self.Store_Fwd_Blk.compute(EV) + self.L1_Latency_Dependency.compute(EV) + self.Split_Loads.compute(EV) + self.FB_Full.compute(EV)))))
self.thresh = (val > 20)
return val
# Total pipeline cost of external Memory- or Cache-Latency related bottlenecks
def Data_Cache_Memory_Latency(self, EV, level):
val = 100 *((self.Memory_Bound.compute(EV) * (self.DRAM_Bound.compute(EV) / (self.DRAM_Bound.compute(EV) + self.L2_Bound.compute(EV) + self.L3_Bound.compute(EV) + self.Store_Bound.compute(EV) + self.L1_Bound.compute(EV))) * (self.MEM_Latency.compute(EV) / (self.MEM_Bandwidth.compute(EV) + self.MEM_Latency.compute(EV)))) + (self.Memory_Bound.compute(EV) * (self.L3_Bound.compute(EV) / (self.DRAM_Bound.compute(EV) + self.L2_Bound.compute(EV) + self.L3_Bound.compute(EV) + self.Store_Bound.compute(EV) + self.L1_Bound.compute(EV))) * (self.L3_Hit_Latency.compute(EV) / (self.Data_Sharing.compute(EV) + self.Contested_Accesses.compute(EV) + self.L3_Hit_Latency.compute(EV) + self.SQ_Full.compute(EV)))) + (self.Memory_Bound.compute(EV) * self.L2_Bound.compute(EV) / (self.DRAM_Bound.compute(EV) + self.L2_Bound.compute(EV) + self.L3_Bound.compute(EV) + self.Store_Bound.compute(EV) + self.L1_Bound.compute(EV))) + (self.Memory_Bound.compute(EV) * (self.L1_Bound.compute(EV) / (self.DRAM_Bound.compute(EV) + self.L2_Bound.compute(EV) + self.L3_Bound.compute(EV) + self.Store_Bound.compute(EV) + self.L1_Bound.compute(EV))) * (self.L1_Latency_Dependency.compute(EV) / (self.DTLB_Load.compute(EV) + self.Lock_Latency.compute(EV) + self.Store_Fwd_Blk.compute(EV) + self.L1_Latency_Dependency.compute(EV) + self.Split_Loads.compute(EV) + self.FB_Full.compute(EV)))) + (self.Memory_Bound.compute(EV) * (self.L1_Bound.compute(EV) / (self.DRAM_Bound.compute(EV) + self.L2_Bound.compute(EV) + self.L3_Bound.compute(EV) + self.Store_Bound.compute(EV) + self.L1_Bound.compute(EV))) * (self.Lock_Latency.compute(EV) / (self.DTLB_Load.compute(EV) + self.Lock_Latency.compute(EV) + self.Store_Fwd_Blk.compute(EV) + self.L1_Latency_Dependency.compute(EV) + self.Split_Loads.compute(EV) + self.FB_Full.compute(EV)))) + (self.Memory_Bound.compute(EV) * (self.L1_Bound.compute(EV) / (self.DRAM_Bound.compute(EV) + self.L2_Bound.compute(EV) + self.L3_Bound.compute(EV) + self.Store_Bound.compute(EV) + self.L1_Bound.compute(EV))) * (self.Split_Loads.compute(EV) / (self.DTLB_Load.compute(EV) + self.Lock_Latency.compute(EV) + self.Store_Fwd_Blk.compute(EV) + self.L1_Latency_Dependency.compute(EV) + self.Split_Loads.compute(EV) + self.FB_Full.compute(EV)))) + (self.Memory_Bound.compute(EV) * (self.Store_Bound.compute(EV) / (self.DRAM_Bound.compute(EV) + self.L2_Bound.compute(EV) + self.L3_Bound.compute(EV) + self.Store_Bound.compute(EV) + self.L1_Bound.compute(EV))) * (self.Split_Stores.compute(EV) / (self.False_Sharing.compute(EV) + self.Store_Latency.compute(EV) + self.Streaming_Stores.compute(EV) + self.DTLB_Store.compute(EV) + self.Split_Stores.compute(EV)))) + (self.Memory_Bound.compute(EV) * (self.Store_Bound.compute(EV) / (self.DRAM_Bound.compute(EV) + self.L2_Bound.compute(EV) + self.L3_Bound.compute(EV) + self.Store_Bound.compute(EV) + self.L1_Bound.compute(EV))) * (self.Store_Latency.compute(EV) / (self.False_Sharing.compute(EV) + self.Store_Latency.compute(EV) + self.Streaming_Stores.compute(EV) + self.DTLB_Store.compute(EV) + self.Split_Stores.compute(EV)))))
self.thresh = (val > 20)
return val
# Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)
def Memory_Data_TLBs(self, EV, level):
val = 100 *((self.Memory_Bound.compute(EV) * (self.L1_Bound.compute(EV) / (self.DRAM_Bound.compute(EV) + self.L2_Bound.compute(EV) + self.L3_Bound.compute(EV) + self.Store_Bound.compute(EV) + self.L1_Bound.compute(EV))) * (self.DTLB_Load.compute(EV) / (self.DTLB_Load.compute(EV) + self.Lock_Latency.compute(EV) + self.Store_Fwd_Blk.compute(EV) + self.L1_Latency_Dependency.compute(EV) + self.Split_Loads.compute(EV) + self.FB_Full.compute(EV)))) + (self.Memory_Bound.compute(EV) * (self.Store_Bound.compute(EV) / (self.DRAM_Bound.compute(EV) + self.L2_Bound.compute(EV) + self.L3_Bound.compute(EV) + self.Store_Bound.compute(EV) + self.L1_Bound.compute(EV))) * (self.DTLB_Store.compute(EV) / (self.False_Sharing.compute(EV) + self.Store_Latency.compute(EV) + self.Streaming_Stores.compute(EV) + self.DTLB_Store.compute(EV) + self.Split_Stores.compute(EV)))))
self.thresh = (val > 20)
return val
# Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors)
def Memory_Synchronization(self, EV, level):
val = 100 *(self.Memory_Bound.compute(EV) * ((self.L3_Bound.compute(EV) / (self.DRAM_Bound.compute(EV) + self.L2_Bound.compute(EV) + self.L3_Bound.compute(EV) + self.Store_Bound.compute(EV) + self.L1_Bound.compute(EV))) * (self.Contested_Accesses.compute(EV) + self.Data_Sharing.compute(EV)) / (self.Data_Sharing.compute(EV) + self.Contested_Accesses.compute(EV) + self.L3_Hit_Latency.compute(EV) + self.SQ_Full.compute(EV)) + (self.Store_Bound.compute(EV) / (self.DRAM_Bound.compute(EV) + self.L2_Bound.compute(EV) + self.L3_Bound.compute(EV) + self.Store_Bound.compute(EV) + self.L1_Bound.compute(EV))) * self.False_Sharing.compute(EV) / ((self.False_Sharing.compute(EV) + self.Store_Latency.compute(EV) + self.Streaming_Stores.compute(EV) + self.DTLB_Store.compute(EV) + self.Split_Stores.compute(EV)) - self.Store_Latency.compute(EV))) + self.Machine_Clears.compute(EV) * (1 - self.Other_Nukes.compute(EV) / (self.Other_Nukes.compute(EV))))
self.thresh = (val > 10)
return val
# Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy.
def Compute_Bound_Est(self, EV, level):
val = 100 *((self.Core_Bound.compute(EV) * self.Divider.compute(EV) / (self.Divider.compute(EV) + self.Ports_Utilization.compute(EV) + self.Serializing_Operation.compute(EV))) + (self.Core_Bound.compute(EV) * (self.Ports_Utilization.compute(EV) / (self.Divider.compute(EV) + self.Ports_Utilization.compute(EV) + self.Serializing_Operation.compute(EV))) * (self.Ports_Utilized_3m.compute(EV) / (self.Ports_Utilized_2.compute(EV) + self.Ports_Utilized_3m.compute(EV) + self.Ports_Utilized_1.compute(EV) + self.Ports_Utilized_0.compute(EV)))))
self.thresh = (val > 20)
return val
# Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments)
def Irregular_Overhead(self, EV, level):
val = 100 *(Assist_Frontend(self, EV, level) + Umisp(self, EV, level) * self.Branch_Mispredicts.compute(EV) + (self.Machine_Clears.compute(EV) * self.Other_Nukes.compute(EV) / (self.Other_Nukes.compute(EV))) + Serialize_Core(self, EV, level) + Assist_Retired(self, EV, level))
self.thresh = (val > 10)
return val
# Total pipeline cost of remaining bottlenecks in the back-end. Examples include data-dependencies (Core Bound when Low ILP) and other unlisted memory-related stalls.
def Other_Bottlenecks(self, EV, level):
val = 100 -(Big_Code(self, EV, level) + Instruction_Fetch_BW(self, EV, level) + Mispredictions(self, EV, level) + Data_Cache_Memory_Bandwidth(self, EV, level) + Data_Cache_Memory_Latency(self, EV, level) + Memory_Data_TLBs(self, EV, level) + Memory_Synchronization(self, EV, level) + Compute_Bound_Est(self, EV, level) + Irregular_Overhead(self, EV, level) + Branching_Overhead(self, EV, level) + Useful_Work(self, EV, level))
self.thresh = (val > 20)
return val
# Total pipeline cost of instructions used for program control-flow - a subset of the Retiring category in TMA. Examples include function calls; loops and alignments. (A lower bound). Consider Loop Unrolling or function inlining optimizations
def Branching_Overhead(self, EV, level):
val = 100 * Branching_Retired(self, EV, level)
self.thresh = (val > 5)
return val
# Total pipeline cost of "useful operations" - the portion of Retiring category not covered by Branching_Overhead nor Irregular_Overhead.
def Useful_Work(self, EV, level):
val = 100 *(self.Retiring.compute(EV) - Branching_Retired(self, EV, level) - Assist_Retired(self, EV, level))
self.thresh = (val > 20)
return val
# Probability of Core Bound bottleneck hidden by SMT-profiling artifacts. Tip: consider analysis with SMT disabled
def Core_Bound_Likely(self, EV, level):
val = 100 *(1 - self.Core_Bound.compute(EV) / self.Ports_Utilization.compute(EV) if self.Core_Bound.compute(EV)< self.Ports_Utilization.compute(EV) else 1) if SMT_2T_Utilization(self, EV, level)> 0.5 else 0
self.thresh = (val > 0.5)
return val
# Instructions Per Cycle (per Logical Processor)
def IPC(self, EV, level):
return EV("INST_RETIRED.ANY", level) / CLKS(self, EV, level)
# Uops Per Instruction
def UopPI(self, EV, level):
val = Retired_Slots(self, EV, level) / EV("INST_RETIRED.ANY", level)
self.thresh = (val > 1.05)
return val
# Uops per taken branch
def UpTB(self, EV, level):
val = Retired_Slots(self, EV, level) / EV("BR_INST_RETIRED.NEAR_TAKEN", level)
self.thresh = val < Pipeline_Width * 1.5
return val
# Cycles Per Instruction (per Logical Processor)
def CPI(self, EV, level):
return 1 / IPC(self, EV, level)
# Per-Logical Processor actual clocks when the Logical Processor is active.
def CLKS(self, EV, level):
return EV("CPU_CLK_UNHALTED.THREAD", level)
# Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)
def SLOTS(self, EV, level):
return EV("TOPDOWN.SLOTS", level) if topdown_use_fixed else EV("TOPDOWN.SLOTS", level)
# Fraction of Physical Core issue-slots utilized by this Logical Processor
def Slots_Utilization(self, EV, level):
return SLOTS(self, EV, level) / (EV("TOPDOWN.SLOTS:percore", level) / 2) if smt_enabled else 1
# The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of "execute" at rename stage.
def Execute_per_Issue(self, EV, level):
return EV("UOPS_EXECUTED.THREAD", level) / EV("UOPS_ISSUED.ANY", level)
# Instructions Per Cycle across hyper-threads (per physical core)
def CoreIPC(self, EV, level):
return EV("INST_RETIRED.ANY", level) / CORE_CLKS(self, EV, level)
# Floating Point Operations Per Cycle
def FLOPc(self, EV, level):
return FLOP_Count(self, EV, level) / CORE_CLKS(self, EV, level)
# Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to Fused-Multiply Add use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common.
def FP_Arith_Utilization(self, EV, level):
return (EV("FP_ARITH_DISPATCHED.PORT_0", level) + EV("FP_ARITH_DISPATCHED.PORT_1", level) + EV("FP_ARITH_DISPATCHED.PORT_5", level)) / (2 * CORE_CLKS(self, EV, level))
# Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor)
def ILP(self, EV, level):
return EV("UOPS_EXECUTED.THREAD", level) / EV("UOPS_EXECUTED.THREAD:c1", level)
# uops Executed per Cycle
def EPC(self, EV, level):
return EV("UOPS_EXECUTED.THREAD", level) / CLKS(self, EV, level)
# Core actual clocks when any Logical Processor is active on the Physical Core
def CORE_CLKS(self, EV, level):
return EV("CPU_CLK_UNHALTED.DISTRIBUTED", level) if smt_enabled else CLKS(self, EV, level)
# Instructions per Load (lower number means higher occurrence rate). Tip: reduce memory accesses. #Link Opt Guide section: Minimize Register Spills
def IpLoad(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / EV("MEM_INST_RETIRED.ALL_LOADS", level)
self.thresh = (val < 3)
return val
# Instructions per Store (lower number means higher occurrence rate). Tip: reduce memory accesses. #Link Opt Guide section: Minimize Register Spills
def IpStore(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / EV("MEM_INST_RETIRED.ALL_STORES", level)
self.thresh = (val < 8)
return val
# Instructions per Branch (lower number means higher occurrence rate)
def IpBranch(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / EV("BR_INST_RETIRED.ALL_BRANCHES", level)
self.thresh = (val < 8)
return val
# Instructions per (near) call (lower number means higher occurrence rate)
def IpCall(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / EV("BR_INST_RETIRED.NEAR_CALL", level)
self.thresh = (val < 200)
return val
# Instructions per taken branch
def IpTB(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / EV("BR_INST_RETIRED.NEAR_TAKEN", level)
self.thresh = val < Pipeline_Width * 2 + 1
return val
# Branch instructions per taken branch. . Can be used to approximate PGO-likelihood for non-loopy codes.
def BpTkBranch(self, EV, level):
return EV("BR_INST_RETIRED.ALL_BRANCHES", level) / EV("BR_INST_RETIRED.NEAR_TAKEN", level)
# Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate). Reference: Tuning Performance via Metrics with Expectations. https://doi.org/10.1109/LCA.2019.2916408
def IpFLOP(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / FLOP_Count(self, EV, level)
self.thresh = (val < 10)
return val
# Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW.
def IpArith(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / (FP_Arith_Scalar(self, EV, level) + FP_Arith_Vector(self, EV, level))
self.thresh = (val < 10)
return val
# Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.
def IpArith_Scalar_SP(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / EV("FP_ARITH_INST_RETIRED.SCALAR_SINGLE", level)
self.thresh = (val < 10)
return val
# Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.
def IpArith_Scalar_DP(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / EV("FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", level)
self.thresh = (val < 10)
return val
# Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.
def IpArith_AVX128(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / (EV("FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", level) + EV("FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", level))
self.thresh = (val < 10)
return val
# Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.
def IpArith_AVX256(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / (EV("FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", level) + EV("FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", level))
self.thresh = (val < 10)
return val
# Instructions per PAUSE (lower number means higher occurrence rate)
def IpPause(self, EV, level):
return Instructions(self, EV, level) / EV("CPU_CLK_UNHALTED.PAUSE_INST", level)
# Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)
def IpSWPF(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / EV("SW_PREFETCH_ACCESS.ANY", level)
self.thresh = (val < 100)
return val
# Total number of retired Instructions
def Instructions(self, EV, level):
return EV("INST_RETIRED.ANY", level)
# Average number of Uops retired in cycles where at least one uop has retired.
def Retire(self, EV, level):
return Retired_Slots(self, EV, level) / EV("UOPS_RETIRED.SLOTS:c1", level)
# Estimated fraction of retirement-cycles dealing with repeat instructions
def Strings_Cycles(self, EV, level):
val = EV("INST_RETIRED.REP_ITERATION", level) / EV("UOPS_RETIRED.SLOTS:c1", level)
self.thresh = (val > 0.1)
return val
# Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)
def IpAssist(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / EV("ASSISTS.ANY", level)
self.thresh = (val < 100000)
return val
# Mem;Backend;CacheHits
def Execute(self, EV, level):
return EV("UOPS_EXECUTED.THREAD", level) / Execute_Cycles(self, EV, level)
# Average number of uops fetched from LSD per cycle
def Fetch_LSD(self, EV, level):
return EV("LSD.UOPS", level) / EV("LSD.CYCLES_ACTIVE", level)
# Average number of uops fetched from DSB per cycle
def Fetch_DSB(self, EV, level):
return EV("IDQ.DSB_UOPS", level) / EV("IDQ.DSB_CYCLES_ANY", level)
# Average number of uops fetched from MITE per cycle
def Fetch_MITE(self, EV, level):
return EV("IDQ.MITE_UOPS", level) / EV("IDQ.MITE_CYCLES_ANY", level)
# Average number of Uops issued by front-end when it issued something
def Fetch_UpC(self, EV, level):
return EV("UOPS_ISSUED.ANY", level) / EV("UOPS_ISSUED.ANY:c1", level)
# Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache)
def LSD_Coverage(self, EV, level):
return EV("LSD.UOPS", level) / Fetched_Uops(self, EV, level)
# Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). See section 'Decoded ICache' in Optimization Manual. http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html
def DSB_Coverage(self, EV, level):
val = EV("IDQ.DSB_UOPS", level) / Fetched_Uops(self, EV, level)
self.thresh = (val < 0.7) and HighIPC(self, EV, 1)
return val
# Average number of cycles the front-end was delayed due to an Unknown Branch detection. See Unknown_Branches node.
def Unknown_Branch_Cost(self, EV, level):
return EV("INT_MISC.UNKNOWN_BRANCH_CYCLES", level) / EV("INT_MISC.UNKNOWN_BRANCH_CYCLES:c1:e1", level)
# Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.
def DSB_Switch_Cost(self, EV, level):
return EV("DSB2MITE_SWITCHES.PENALTY_CYCLES", level) / EV("DSB2MITE_SWITCHES.PENALTY_CYCLES:c1:e1", level)
# Taken Branches retired Per Cycle
def TBpC(self, EV, level):
return EV("BR_INST_RETIRED.NEAR_TAKEN", level) / CLKS(self, EV, level)
# Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.
def DSB_Misses(self, EV, level):
val = 100 *(self.Fetch_Latency.compute(EV) * self.DSB_Switches.compute(EV) / (self.Branch_Resteers.compute(EV) + self.MS_Switches.compute(EV) + self.ICache_Misses.compute(EV) + self.LCP.compute(EV) + self.ITLB_Misses.compute(EV) + self.DSB_Switches.compute(EV)) + self.Fetch_Bandwidth.compute(EV) * self.MITE.compute(EV) / (self.MS.compute(EV) + self.MITE.compute(EV) + self.LSD.compute(EV) + self.DSB.compute(EV)))
self.thresh = (val > 10)
return val
# Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck.
def DSB_Bandwidth(self, EV, level):
val = 100 *(self.Frontend_Bound.compute(EV) * (self.Fetch_Bandwidth.compute(EV) / (self.Fetch_Bandwidth.compute(EV) + self.Fetch_Latency.compute(EV))) * (self.DSB.compute(EV) / (self.MS.compute(EV) + self.MITE.compute(EV) + self.LSD.compute(EV) + self.DSB.compute(EV))))
self.thresh = (val > 10)
return val
# This metric represents fraction of cycles the CPU retirement was stalled likely due to retired DSB misses
def DSB_Switches_Ret(self, EV, level):
val = EV("FRONTEND_RETIRED.ANY_DSB_MISS", level) * EV("FRONTEND_RETIRED.ANY_DSB_MISS", 999) / CLKS(self, EV, level)
self.thresh = (val > 0.05)
return val
# This metric represents fraction of cycles the CPU retirement was stalled likely due to retired operations that invoke the Microcode Sequencer
def MS_Latency_Ret(self, EV, level):
val = EV("FRONTEND_RETIRED.MS_FLOWS", level) * EV("FRONTEND_RETIRED.MS_FLOWS", 999) / CLKS(self, EV, level)
self.thresh = (val > 0.05)
return val
# This metric represents fraction of cycles the CPU retirement was stalled likely due to retired branches who got branch address clears
def Unknown_Branches_Ret(self, EV, level):
return EV("FRONTEND_RETIRED.UNKNOWN_BRANCH", level) * EV("FRONTEND_RETIRED.UNKNOWN_BRANCH", 999) / CLKS(self, EV, level)
# Average Latency for L1 instruction cache misses
def ICache_Miss_Latency(self, EV, level):
return EV("ICACHE_DATA.STALLS", level) / EV("ICACHE_DATA.STALL_PERIODS", level)
# Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck.
def IC_Misses(self, EV, level):
val = 100 *(self.Fetch_Latency.compute(EV) * self.ICache_Misses.compute(EV) / (self.Branch_Resteers.compute(EV) + self.MS_Switches.compute(EV) + self.ICache_Misses.compute(EV) + self.LCP.compute(EV) + self.ITLB_Misses.compute(EV) + self.DSB_Switches.compute(EV)))
self.thresh = (val > 5)
return val
# Instructions per non-speculative DSB miss (lower number means higher occurrence rate)
def IpDSB_Miss_Ret(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / EV("FRONTEND_RETIRED.ANY_DSB_MISS", level)
self.thresh = (val < 50)
return val
# Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)
def IpUnknown_Branch(self, EV, level):
return Instructions(self, EV, level) / EV("BACLEARS.ANY", level)
# L2 cache true code cacheline misses per kilo instruction
def L2MPKI_Code(self, EV, level):
return 1000 * EV("FRONTEND_RETIRED.L2_MISS", level) / EV("INST_RETIRED.ANY", level)
# L2 cache speculative code cacheline misses per kilo instruction
def L2MPKI_Code_All(self, EV, level):
return 1000 * EV("L2_RQSTS.CODE_RD_MISS", level) / EV("INST_RETIRED.ANY", level)
# Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)
def IpMispredict(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / EV("BR_MISP_RETIRED.ALL_BRANCHES", level)
self.thresh = (val < 200)
return val
# Instructions per retired Mispredicts for conditional non-taken branches (lower number means higher occurrence rate).
def IpMisp_Cond_Ntaken(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / EV("BR_MISP_RETIRED.COND_NTAKEN", level)
self.thresh = (val < 200)
return val
# Instructions per retired Mispredicts for conditional taken branches (lower number means higher occurrence rate).
def IpMisp_Cond_Taken(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / EV("BR_MISP_RETIRED.COND_TAKEN", level)
self.thresh = (val < 200)
return val
# Instructions per retired Mispredicts for return branches (lower number means higher occurrence rate).
def IpMisp_Ret(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / EV("BR_MISP_RETIRED.RET", level)
self.thresh = (val < 500)
return val
# Instructions per retired Mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).
def IpMisp_Indirect(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / EV("BR_MISP_RETIRED.INDIRECT", level)
self.thresh = (val < 1000)
return val
# Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)
def Branch_Misprediction_Cost(self, EV, level):
return Mispredictions(self, EV, level) * SLOTS(self, EV, level) / Pipeline_Width / EV("BR_MISP_RETIRED.ALL_BRANCHES", level) / 100
# Speculative to Retired ratio of all clears (covering Mispredicts and nukes)
def Spec_Clears_Ratio(self, EV, level):
return EV("INT_MISC.CLEARS_COUNT", level) / (EV("BR_MISP_RETIRED.ALL_BRANCHES", level) + EV("MACHINE_CLEARS.COUNT", level))
# Fraction of branches that are non-taken conditionals
def Cond_NT(self, EV, level):
return EV("BR_INST_RETIRED.COND_NTAKEN", level) / EV("BR_INST_RETIRED.ALL_BRANCHES", level)
# Fraction of branches that are taken conditionals
def Cond_TK(self, EV, level):
return EV("BR_INST_RETIRED.COND_TAKEN", level) / EV("BR_INST_RETIRED.ALL_BRANCHES", level)
# Fraction of branches that are CALL or RET
def CallRet(self, EV, level):
return (EV("BR_INST_RETIRED.NEAR_CALL", level) + EV("BR_INST_RETIRED.NEAR_RETURN", level)) / EV("BR_INST_RETIRED.ALL_BRANCHES", level)
# Fraction of branches that are unconditional (direct or indirect) jumps
def Jump(self, EV, level):
return Br_DoI_Jumps(self, EV, level) / EV("BR_INST_RETIRED.ALL_BRANCHES", level)
# Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)
def Other_Branches(self, EV, level):
return 1 -(Cond_NT(self, EV, level) + Cond_TK(self, EV, level) + CallRet(self, EV, level) + Jump(self, EV, level))
# Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)
def Load_Miss_Real_Latency(self, EV, level):
return EV("L1D_PEND_MISS.PENDING", level) / EV("MEM_LOAD_COMPLETED.L1_MISS_ANY", level)
# Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)
def MLP(self, EV, level):
return EV("L1D_PEND_MISS.PENDING", level) / EV("L1D_PEND_MISS.PENDING_CYCLES", level)
# L1 cache true misses per kilo instruction for retired demand loads
def L1MPKI(self, EV, level):
return 1000 * EV("MEM_LOAD_RETIRED.L1_MISS", level) / EV("INST_RETIRED.ANY", level)
# L1 cache true misses per kilo instruction for all demand loads (including speculative)
def L1MPKI_Load(self, EV, level):
return 1000 * EV("L2_RQSTS.ALL_DEMAND_DATA_RD", level) / EV("INST_RETIRED.ANY", level)
# L2 cache true misses per kilo instruction for retired demand loads
def L2MPKI(self, EV, level):
return 1000 * EV("MEM_LOAD_RETIRED.L2_MISS", level) / EV("INST_RETIRED.ANY", level)
# L2 cache true misses per kilo instruction for all request types (including speculative)
def L2MPKI_All(self, EV, level):
return 1000 * EV("L2_RQSTS.MISS", level) / EV("INST_RETIRED.ANY", level)
# L2 cache true misses per kilo instruction for all demand loads (including speculative)
def L2MPKI_Load(self, EV, level):
return 1000 * EV("L2_RQSTS.DEMAND_DATA_RD_MISS", level) / EV("INST_RETIRED.ANY", level)
# Offcore requests (L2 cache miss) per kilo instruction for demand RFOs
def L2MPKI_RFO(self, EV, level):
return 1000 * EV("L2_RQSTS.RFO_MISS", level) / EV("INST_RETIRED.ANY", level)
# L2 cache hits per kilo instruction for all request types (including speculative)
def L2HPKI_All(self, EV, level):
return 1000 *(EV("L2_RQSTS.REFERENCES", level) - EV("L2_RQSTS.MISS", level)) / EV("INST_RETIRED.ANY", level)
# L2 cache hits per kilo instruction for all demand loads (including speculative)
def L2HPKI_Load(self, EV, level):
return 1000 * EV("L2_RQSTS.DEMAND_DATA_RD_HIT", level) / EV("INST_RETIRED.ANY", level)
# L3 cache true misses per kilo instruction for retired demand loads
def L3MPKI(self, EV, level):
return 1000 * EV("MEM_LOAD_RETIRED.L3_MISS", level) / EV("INST_RETIRED.ANY", level)
# Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)
def FB_HPKI(self, EV, level):
return 1000 * EV("MEM_LOAD_RETIRED.FB_HIT", level) / EV("INST_RETIRED.ANY", level)
# Average per-thread data fill bandwidth to the L1 data cache [GB / sec]
def L1D_Cache_Fill_BW(self, EV, level):
return 64 * EV("L1D.REPLACEMENT", level) / OneBillion / Time(self, EV, level)
# Average per-thread data fill bandwidth to the L2 cache [GB / sec]
def L2_Cache_Fill_BW(self, EV, level):
return 64 * EV("L2_LINES_IN.ALL", level) / OneBillion / Time(self, EV, level)
# Average per-thread data fill bandwidth to the L3 cache [GB / sec]
def L3_Cache_Fill_BW(self, EV, level):
return 64 * EV("LONGEST_LAT_CACHE.MISS", level) / OneBillion / Time(self, EV, level)
# Average per-thread data access bandwidth to the L3 cache [GB / sec]
def L3_Cache_Access_BW(self, EV, level):
return 64 * EV("OFFCORE_REQUESTS.ALL_REQUESTS", level) / OneBillion / Time(self, EV, level)
# Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses
def Page_Walks_Utilization(self, EV, level):
val = (EV("ITLB_MISSES.WALK_PENDING", level) + EV("DTLB_LOAD_MISSES.WALK_PENDING", level) + EV("DTLB_STORE_MISSES.WALK_PENDING", level)) / (4 * CORE_CLKS(self, EV, level))
self.thresh = (val > 0.5)
return val
# STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)
def Code_STLB_MPKI(self, EV, level):
return 1000 * EV("ITLB_MISSES.WALK_COMPLETED", level) / EV("INST_RETIRED.ANY", level)
# STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)
def Load_STLB_MPKI(self, EV, level):
return 1000 * EV("DTLB_LOAD_MISSES.WALK_COMPLETED", level) / EV("INST_RETIRED.ANY", level)
# STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)
def Store_STLB_MPKI(self, EV, level):
return 1000 * EV("DTLB_STORE_MISSES.WALK_COMPLETED", level) / EV("INST_RETIRED.ANY", level)
# This metric represents fraction of cycles the CPU retirement was stalled likely due to STLB misses by demand loads
def Load_STLB_Miss_Ret(self, EV, level):
val = EV("MEM_INST_RETIRED.STLB_MISS_LOADS", level) * EV("MEM_INST_RETIRED.STLB_MISS_LOADS", 999) / CLKS(self, EV, level)
self.thresh = (val > 0.05)
return val
# This metric represents fraction of cycles the CPU retirement was stalled likely due to STLB misses by demand stores
def Store_STLB_Miss_Ret(self, EV, level):
val = EV("MEM_INST_RETIRED.STLB_MISS_STORES", level) * EV("MEM_INST_RETIRED.STLB_MISS_STORES", 999) / CLKS(self, EV, level)
self.thresh = (val > 0.05)
return val
# Average per-core data fill bandwidth to the L1 data cache [GB / sec]
def L1D_Cache_Fill_BW_2T(self, EV, level):
return L1D_Cache_Fill_BW(self, EV, level)
# Average per-core data fill bandwidth to the L2 cache [GB / sec]
def L2_Cache_Fill_BW_2T(self, EV, level):
return L2_Cache_Fill_BW(self, EV, level)
# Average per-core data fill bandwidth to the L3 cache [GB / sec]
def L3_Cache_Fill_BW_2T(self, EV, level):
return L3_Cache_Fill_BW(self, EV, level)
# Average per-core data access bandwidth to the L3 cache [GB / sec]
def L3_Cache_Access_BW_2T(self, EV, level):
return L3_Cache_Access_BW(self, EV, level)
# Rate of L2 HW prefetched lines that were not used by demand accesses
def Useless_HWPF(self, EV, level):
val = EV("L2_LINES_OUT.USELESS_HWPF", level) / (EV("L2_LINES_OUT.SILENT", level) + EV("L2_LINES_OUT.NON_SILENT", level))
self.thresh = (val > 0.15)
return val
# Average Latency for L2 cache miss demand Loads
def Load_L2_Miss_Latency(self, EV, level):
return EV("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", level) / EV("OFFCORE_REQUESTS.DEMAND_DATA_RD", level)
# Average Latency for L3 cache miss demand Loads
def Load_L3_Miss_Latency(self, EV, level):
return EV("OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", level) / EV("OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", level)
# Average Parallel L2 cache miss demand Loads
def Load_L2_MLP(self, EV, level):
return EV("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", level) / EV("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD:c1", level)
# Average Parallel L2 cache miss data reads
def Data_L2_MLP(self, EV, level):
return EV("OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", level) / EV("OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", level)
# Un-cacheable retired load per kilo instruction
def UC_Load_PKI(self, EV, level):
return 1000 * EV("MEM_LOAD_MISC_RETIRED.UC", level) / EV("INST_RETIRED.ANY", level)
# "Bus lock" per kilo instruction
def Bus_Lock_PKI(self, EV, level):
return 1000 * EV("SQ_MISC.BUS_LOCK", level) / EV("INST_RETIRED.ANY", level)
# Average CPU Utilization (percentage)
def CPU_Utilization(self, EV, level):
return CPUs_Utilized(self, EV, level) / Num_CPUs(self, EV, level)
# Average number of utilized CPUs
def CPUs_Utilized(self, EV, level):
return EV("CPU_CLK_UNHALTED.REF_TSC", level) / EV("msr/tsc/", 0)
# Measured Average Core Frequency for unhalted processors [GHz]
def Core_Frequency(self, EV, level):
return Turbo_Utilization(self, EV, level) * EV("msr/tsc/", 0) / OneBillion / Time(self, EV, level)
# Measured Average Uncore Frequency for the SoC [GHz]
def Uncore_Frequency(self, EV, level):
return Socket_CLKS(self, EV, level) / 1e9 / Time(self, EV, level)
# Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width
def GFLOPs(self, EV, level):
return (FLOP_Count(self, EV, level) / OneBillion) / Time(self, EV, level)
# Average Frequency Utilization relative nominal frequency
def Turbo_Utilization(self, EV, level):
return CLKS(self, EV, level) / EV("CPU_CLK_UNHALTED.REF_TSC", level)
# Fraction of cycles where both hardware Logical Processors were active
def SMT_2T_Utilization(self, EV, level):
return 1 - EV("CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", level) / EV("CPU_CLK_UNHALTED.REF_DISTRIBUTED", level) if smt_enabled else 0
# Fraction of cycles spent in the Operating System (OS) Kernel mode
def Kernel_Utilization(self, EV, level):
val = EV("CPU_CLK_UNHALTED.THREAD_P:SUP", level) / EV("CPU_CLK_UNHALTED.THREAD", level)
self.thresh = (val > 0.05)
return val
# Cycles Per Instruction for the Operating System (OS) Kernel mode
def Kernel_CPI(self, EV, level):
return EV("CPU_CLK_UNHALTED.THREAD_P:SUP", level) / EV("INST_RETIRED.ANY_P:SUP", level)
# Fraction of cycles the processor is waiting yet unhalted; covering legacy PAUSE instruction, as well as C0.1 / C0.2 power-performance optimized states. Sample code of TPAUSE: https://github.com/torvalds/linux/blob/master/arch/x86/lib/delay.c#L105. If running on Linux, please check the power control interface: https://github.com/torvalds/linux/blob/master/arch/x86/kernel/cpu/umwait.c and https://github.com/torvalds/linux/blob/master/Documentation/ABI/testing/sysfs-devices-system-cpu#L587
def C0_Wait(self, EV, level):
val = EV("CPU_CLK_UNHALTED.C0_WAIT", level) / CLKS(self, EV, level)
self.thresh = (val > 0.05)
return val
# Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches
def MEM_Parallel_Reads(self, EV, level):
return EV("UNC_ARB_DAT_OCCUPANCY.RD", level) / EV("UNC_ARB_DAT_OCCUPANCY.RD:c1", level)
# Run duration time in seconds
def Time(self, EV, level):
val = EV("interval-s", 0)
self.thresh = (val < 1)
return val
# Socket actual clocks when any core is active on that socket
def Socket_CLKS(self, EV, level):
return EV("UNC_CLOCK.SOCKET", level)
# Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]
def IpFarBranch(self, EV, level):
val = EV("INST_RETIRED.ANY", level) / EV("BR_INST_RETIRED.FAR_BRANCH:USER", level)
self.thresh = (val < 1000000)
return val
# Event groups
class Frontend_Bound:
name = "Frontend_Bound"
domain = "Slots"
area = "FE"
level = 1
htoff = False
sample = ['FRONTEND_RETIRED.LATENCY_GE_4:pp']
errcount = 0
sibling = None
metricgroup = frozenset(['BvFB', 'BvIO', 'TmaL1', 'PGO'])
maxval = None
def compute(self, EV):
try:
self.val = (EV("PERF_METRICS.FRONTEND_BOUND", 1) / EV("TOPDOWN.SLOTS", 1)) / PERF_METRICS_SUM(self, EV, 1) - EV("INT_MISC.UOP_DROPPING", 1) / SLOTS(self, EV, 1) if topdown_use_fixed else(EV("IDQ_BUBBLES.CORE", 1) - EV("INT_MISC.UOP_DROPPING", 1)) / SLOTS(self, EV, 1)
self.thresh = (self.val > 0.15)
except ZeroDivisionError:
handle_error(self, "Frontend_Bound zero division")
return self.val
desc = """
This category represents fraction of slots where the
processor's Frontend undersupplies its Backend. Frontend
denotes the first part of the processor core responsible to
fetch operations that are executed later on by the Backend
part. Within the Frontend; a branch predictor predicts the
next address to fetch; cache-lines are fetched from the
memory subsystem; parsed into instructions; and lastly
decoded into micro-operations (uops). Ideally the Frontend
can issue Pipeline_Width uops every cycle to the Backend.
Frontend Bound denotes unutilized issue-slots when there is
no Backend stall; i.e. bubbles where Frontend delivered no
uops while Backend could have accepted them. For example;
stalls due to instruction-cache misses would be categorized
under Frontend Bound."""
class Fetch_Latency:
name = "Fetch_Latency"
domain = "Slots"
area = "FE"
level = 2
htoff = False
sample = ['FRONTEND_RETIRED.LATENCY_GE_16:pp', 'FRONTEND_RETIRED.LATENCY_GE_8:pp']
errcount = 0
sibling = None
metricgroup = frozenset(['Frontend', 'TmaL2'])
maxval = None
def compute(self, EV):
try:
self.val = ((EV("PERF_METRICS.FETCH_LATENCY", 2) / EV("TOPDOWN.SLOTS", 2)) / PERF_METRICS_SUM(self, EV, 2) - EV("INT_MISC.UOP_DROPPING", 2) / SLOTS(self, EV, 2)) if topdown_use_fixed else(EV("IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE", 2) * Pipeline_Width - EV("INT_MISC.UOP_DROPPING", 2)) / SLOTS(self, EV, 2)
self.thresh = (self.val > 0.1) and self.parent.thresh
except ZeroDivisionError:
handle_error(self, "Fetch_Latency zero division")
return self.val
desc = """
This metric represents fraction of slots the CPU was stalled
due to Frontend latency issues. For example; instruction-
cache misses; iTLB misses or fetch stalls after a branch
misprediction are categorized under Frontend Latency. In
such cases; the Frontend eventually delivers no uops for
some period."""
class ICache_Misses:
name = "ICache_Misses"
domain = "Clocks"
area = "FE"
level = 3
htoff = False
sample = ['FRONTEND_RETIRED.L2_MISS:pp', 'FRONTEND_RETIRED.L1I_MISS:pp']
errcount = 0
sibling = None
metricgroup = frozenset(['BigFootprint', 'BvBC', 'FetchLat', 'IcMiss'])
maxval = None
def compute(self, EV):
try:
self.val = EV("ICACHE_DATA.STALLS", 3) / CLKS(self, EV, 3)
self.thresh = (self.val > 0.05) and self.parent.thresh
except ZeroDivisionError:
handle_error(self, "ICache_Misses zero division")
return self.val
desc = """
This metric represents fraction of cycles the CPU was
stalled due to instruction cache misses.. Using compiler's
Profile-Guided Optimization (PGO) can reduce i-cache misses
through improved hot code layout."""
class Code_L2_Hit:
name = "Code_L2_Hit"
domain = "Clocks_Retired"
area = "FE"
level = 4
htoff = False
sample = []
errcount = 0
sibling = None
metricgroup = frozenset(['IcMiss', 'FetchLat', 'Offcore'])
maxval = None
def compute(self, EV):
try:
self.val = max(0 , EV("FRONTEND_RETIRED.L1I_MISS", 4) * EV("FRONTEND_RETIRED.L1I_MISS", 999) / CLKS(self, EV, 4) - self.Code_L2_Miss.compute(EV))
self.thresh = (self.val > 0.05) and self.parent.thresh
except ZeroDivisionError:
handle_error(self, "Code_L2_Hit zero division")
return self.val
desc = """
This metric estimates fraction of cycles the CPU was stalled
due to instruction cache misses that hit in the L2 cache."""
class Code_L2_Miss:
name = "Code_L2_Miss"
domain = "Clocks_Retired"
area = "FE"
level = 4
htoff = False
sample = []
errcount = 0
sibling = None
metricgroup = frozenset(['IcMiss', 'FetchLat', 'Offcore'])
maxval = None
def compute(self, EV):
try:
self.val = EV("FRONTEND_RETIRED.L2_MISS", 4) * EV("FRONTEND_RETIRED.L2_MISS", 999) / CLKS(self, EV, 4)
self.thresh = (self.val > 0.05) and self.parent.thresh
except ZeroDivisionError:
handle_error(self, "Code_L2_Miss zero division")
return self.val
desc = """
This metric estimates fraction of cycles the CPU was stalled
due to instruction cache misses that miss in the L2 cache."""
class ITLB_Misses:
name = "ITLB_Misses"
domain = "Clocks"
area = "FE"
level = 3
htoff = False
sample = ['FRONTEND_RETIRED.STLB_MISS:pp', 'FRONTEND_RETIRED.ITLB_MISS:pp']
errcount = 0
sibling = None
metricgroup = frozenset(['BigFootprint', 'BvBC', 'FetchLat', 'MemoryTLB'])
maxval = None
def compute(self, EV):
try:
self.val = EV("ICACHE_TAG.STALLS", 3) / CLKS(self, EV, 3)
self.thresh = (self.val > 0.05) and self.parent.thresh
except ZeroDivisionError:
handle_error(self, "ITLB_Misses zero division")
return self.val
desc = """
This metric represents fraction of cycles the CPU was
stalled due to Instruction TLB (ITLB) misses.. Consider
large 2M pages for code (selectively prefer hot large-size
function, due to limited 2M entries). Linux options:
standard binaries use libhugetlbfs; Hfsort.. https://github.
com/libhugetlbfs/libhugetlbfs;https://research.fb.com/public
ations/optimizing-function-placement-for-large-scale-data-
center-applications-2/"""
class Code_STLB_Hit:
name = "Code_STLB_Hit"
domain = "Clocks_Retired"
area = "FE"
level = 4
htoff = False
sample = []
errcount = 0
sibling = None
metricgroup = frozenset(['FetchLat', 'MemoryTLB'])
maxval = None
def compute(self, EV):
try:
self.val = max(0 , EV("FRONTEND_RETIRED.ITLB_MISS", 4) * EV("FRONTEND_RETIRED.ITLB_MISS", 999) / CLKS(self, EV, 4) - self.Code_STLB_Miss.compute(EV))
self.thresh = (self.val > 0.05) and self.parent.thresh
except ZeroDivisionError:
handle_error(self, "Code_STLB_Hit zero division")
return self.val
desc = """
This metric roughly estimates the fraction of cycles where
the (first level) ITLB was missed by instructions fetches,
that later on hit in second-level TLB (STLB)"""
class Code_STLB_Miss:
name = "Code_STLB_Miss"
domain = "Clocks_Retired"
area = "FE"
level = 4
htoff = False
sample = []
errcount = 0
sibling = None
metricgroup = frozenset(['FetchLat', 'MemoryTLB'])
maxval = 1.0
def compute(self, EV):
try:
self.val = EV("FRONTEND_RETIRED.STLB_MISS", 4) * EV("FRONTEND_RETIRED.STLB_MISS", 999) / CLKS(self, EV, 4)
self.thresh = (self.val > 0.05) and self.parent.thresh
except ZeroDivisionError:
handle_error(self, "Code_STLB_Miss zero division")
return self.val
desc = """
This metric estimates the fraction of cycles where the
Second-level TLB (STLB) was missed by instruction fetches,
performing a hardware page walk"""
class Code_STLB_Miss_4K:
name = "Code_STLB_Miss_4K"
domain = "Clocks_Estimated"
area = "FE"
level = 5
htoff = False
sample = []
errcount = 0
sibling = None
metricgroup = frozenset(['FetchLat', 'MemoryTLB'])
maxval = None
def compute(self, EV):
try:
self.val = EV("ITLB_MISSES.WALK_ACTIVE", 5) / CLKS(self, EV, 5) * EV("ITLB_MISSES.WALK_COMPLETED_4K", 5) / (EV("ITLB_MISSES.WALK_COMPLETED_4K", 5) + EV("ITLB_MISSES.WALK_COMPLETED_2M_4M", 5))