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| 1 | +.section .data |
| 2 | + |
| 3 | +/* .globl exposes symbols to the linker, and may be referred to in C code as extern */ |
| 4 | + .globl v_err_reg |
| 5 | + .globl v_err_pc |
| 6 | + .globl v_err_addr |
| 7 | + .globl v_err_ext1 |
| 8 | + .globl v_err_ext2 |
| 9 | + .globl v_err_sr |
| 10 | + .globl v_err_type |
| 11 | + |
| 12 | +/* Used for the crash handler (see error.c and the error handlers below) */ |
| 13 | +v_err_reg: ds.l 16 |
| 14 | +v_err_pc: ds.l 1 |
| 15 | +v_err_addr: ds.l 1 |
| 16 | +v_err_ext1: ds.w 1 |
| 17 | +v_err_ext2: ds.w 1 |
| 18 | +v_err_sr: ds.w 1 |
| 19 | +v_err_type: ds.b 1 |
| 20 | + |
| 21 | +.section .text |
| 22 | + |
| 23 | + .org 0x00000000 /* Forces linker to put us at the beginning */ |
| 24 | + |
| 25 | +RomStart: |
| 26 | + dc.l 0x000000 /* Initial stack pointer address */ |
| 27 | + dc.l _start /* Program start address */ |
| 28 | + dc.l BusError /* Not thrown on MD */ |
| 29 | + dc.l AddressError /* Thrown when a W or L instruction uses an odd address */ |
| 30 | + dc.l IllegalInst /* Thrown when the CPU encounters an invalid instruction */ |
| 31 | + dc.l ZeroDivide /* Thrown when DIV receives a 0 on the left hand side */ |
| 32 | + dc.l 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 |
| 33 | + dc.l 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 |
| 34 | + dc.l ExtInt, 0 /* External Interrupt */ |
| 35 | + dc.l HBlank, 0 /* Horizontal Blank Interrupt */ |
| 36 | + dc.l VBlank, 0 /* Vertical Blank Interrupt */ |
| 37 | + .rept 8 |
| 38 | + dc.l 0, 0, 0, 0 |
| 39 | + .endr |
| 40 | + |
| 41 | +RomHeader: |
| 42 | + .ascii "SEGA MEGA DRIVE " /* First 4 bytes must be "SEGA" */ |
| 43 | + .ascii "GRIND 2022.OCT" /* Copyright and date */ |
| 44 | + .ascii "Example Project " /* JP Name */ |
| 45 | + .ascii "Example Project " /* EN Name */ |
| 46 | + .ascii "GM CHANGEME-XX" /* Serial No. */ |
| 47 | + dc.w 0 |
| 48 | + .ascii "J " /* Controller support */ |
| 49 | + dc.l 0x000000 /* ROM Start */ |
| 50 | + dc.l 0x3FFFFF /* ROM End (4MB) */ |
| 51 | + dc.l 0xFF0000 /* RAM Start */ |
| 52 | + dc.l 0xFFFFFF /* RAM End (64KB) */ |
| 53 | + .ascii "RA" /* "RA" to enable SRAM, " " to disable */ |
| 54 | + dc.w 0xF820 /* SRAM writes to odd bytes */ |
| 55 | + dc.l 0x200001 /* SRAM Start */ |
| 56 | + dc.l 0x20FFFF /* SRAM End (32KB) */ |
| 57 | + .ascii " " |
| 58 | + .ascii " " |
| 59 | + .ascii "JUE " /* Region */ |
| 60 | + |
| 61 | +_start: |
| 62 | + move #0x2700,sr /* Disable interrupts */ |
| 63 | + move.b (0xA10001),d0 /* Check console version */ |
| 64 | + andi.b #0x0F,d0 /* Version 0 = skip TMSS */ |
| 65 | + beq.s NoTMSS |
| 66 | + move.l (0x100),0xA14000 /* Write 'SEGA' to TMSS register */ |
| 67 | +NoTMSS: |
| 68 | + move.w (0xC00004),d0 /* Read VDP status */ |
| 69 | + move.w #0x0100,(0xA11100) /* Halt / Reset Z80 */ |
| 70 | + move.w #0x0100,(0xA11200) |
| 71 | + .globl _hard_reset |
| 72 | +_hard_reset: /* SYS_HardReset() resets sp and jumps here */ |
| 73 | + lea 0xFF0000,a0 /* First RAM address */ |
| 74 | + moveq #0,d0 |
| 75 | + move.w #0x3FFF,d1 /* (Size of RAM - 1) / Size of long */ |
| 76 | +ClearRam: |
| 77 | + move.l d0,(a0)+ |
| 78 | + dbra d1,ClearRam |
| 79 | + lea _stext,a0 /* Start of initialized data (BSS) in ROM */ |
| 80 | + lea 0xFF0000,a1 /* First RAM address */ |
| 81 | + move.l #_sdata,d0 /* (Size of BSS + 1) / 2 */ |
| 82 | + addq.l #1,d0 |
| 83 | + lsr.l #1,d0 |
| 84 | + beq NoCopy |
| 85 | + subq.w #1,d0 /* sub extra iteration */ |
| 86 | +CopyVar: |
| 87 | + move.w (a0)+,(a1)+ /* Copy initialized data to RAM */ |
| 88 | + dbra d0,CopyVar |
| 89 | +NoCopy: |
| 90 | + jsr main /* IT BEGINS */ |
| 91 | + beq.s _hard_reset /* main returned, reset */ |
| 92 | + |
| 93 | +/* Error handling */ |
| 94 | + |
| 95 | +BusError: |
| 96 | + move.b #0,(v_err_type) |
| 97 | + bra.s AddressDump |
| 98 | + |
| 99 | +AddressError: |
| 100 | + move.b #1,(v_err_type) |
| 101 | + bra.s AddressDump |
| 102 | + |
| 103 | +IllegalInst: |
| 104 | + move.b #2,(v_err_type) |
| 105 | + bra.s IllegalDump |
| 106 | + |
| 107 | +ZeroDivide: |
| 108 | + move.b #3,(v_err_type) |
| 109 | + bra.s ZeroDump |
| 110 | + |
| 111 | +AddressDump: |
| 112 | + move.w 4(sp),v_err_ext1 |
| 113 | + move.l 6(sp),v_err_addr |
| 114 | + move.w 10(sp),v_err_ext2 |
| 115 | + move.w 12(sp),v_err_sr |
| 116 | + move.l 14(sp),v_err_pc |
| 117 | + bra.s RegDump |
| 118 | +IllegalDump: |
| 119 | + move.w 10(sp),v_err_ext1 |
| 120 | +ZeroDump: |
| 121 | + move.w 4(sp),v_err_sr |
| 122 | + move.l 6(sp),v_err_pc |
| 123 | +RegDump: |
| 124 | + move.l d0,v_err_reg+0 |
| 125 | + move.l d1,v_err_reg+4 |
| 126 | + move.l d2,v_err_reg+8 |
| 127 | + move.l d3,v_err_reg+12 |
| 128 | + move.l d4,v_err_reg+16 |
| 129 | + move.l d5,v_err_reg+20 |
| 130 | + move.l d6,v_err_reg+24 |
| 131 | + move.l d7,v_err_reg+28 |
| 132 | + move.l a0,v_err_reg+32 |
| 133 | + move.l a1,v_err_reg+36 |
| 134 | + move.l a2,v_err_reg+40 |
| 135 | + move.l a3,v_err_reg+44 |
| 136 | + move.l a4,v_err_reg+48 |
| 137 | + move.l a5,v_err_reg+52 |
| 138 | + move.l a6,v_err_reg+56 |
| 139 | + move.l a7,v_err_reg+60 |
| 140 | + jmp _error |
| 141 | + |
| 142 | +/* Standard interrupts */ |
| 143 | + |
| 144 | +ExtInt: |
| 145 | + rte |
| 146 | + |
| 147 | +HBlank: |
| 148 | + rte |
| 149 | + |
| 150 | +VBlank: |
| 151 | + rte |
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