arch/arm: clang-format changes

Late-arriving clang-format-demanded changes that are too hard to split
and squash into the original patches.  No behavior changes.

Signed-off-by: Andy Ross <[email protected]>

Author: andyross

arch/arm/core/cortex_m/arm-m-switch.c

@@ -233,7 +233,7 @@ static void iciit_fixup(struct k_thread *th, struct hw_frame_base *hw, uint32_t
 		/* Stash original return address, replace with hook */
 		th->arch.iciit_pc = hw->pc;
 		th->arch.iciit_apsr = hw->apsr;
-		hw->pc = (uint32_t) arm_m_iciit_stub;
+		hw->pc = (uint32_t)arm_m_iciit_stub;
 	}
 #endif
 }
@@ -413,7 +413,7 @@ void *arm_m_new_stack(char *base, uint32_t sz, void *entry, void *arg0, void *ar
 	uint32_t *s_top = (uint32_t *)(stack + K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[0]));
 
 	arm_m_exc_lr_ptr = &s_top[-1];
-	arm_m_cs_ptrs.lr_fixup = (void *) (1 | (uint32_t)arm_m_exc_exit); /* thumb bit! */
+	arm_m_cs_ptrs.lr_fixup = (void *)(1 | (uint32_t)arm_m_exc_exit); /* thumb bit! */
 #endif
 
 	baddr = ((uint32_t)base + 7) & ~7;
@@ -457,16 +457,15 @@ bool arm_m_must_switch(void)
 	 */
 	uint32_t pri = _EXC_IRQ_DEFAULT_PRIO;
 
-	__asm__ volatile("msr basepri, %0" :: "r"(pri));
+	__asm__ volatile("msr basepri, %0" ::"r"(pri));
 
 	/* Secure mode transistions can push a non-thread frame to the
 	 * stack.  If not enabled, we already know by construction
 	 * that we're handling the bottom level of the interrupt stack
 	 * and returning to thread mode.
 	 */
-	if ((IS_ENABLED(CONFIG_ARM_SECURE_FIRMWARE) ||
-	    IS_ENABLED(CONFIG_ARM_NONSECURE_FIRMWARE))
-	    && !is_thread_return((uint32_t)arm_m_cs_ptrs.lr_save)) {
+	if ((IS_ENABLED(CONFIG_ARM_SECURE_FIRMWARE) || IS_ENABLED(CONFIG_ARM_NONSECURE_FIRMWARE)) &&
+	    !is_thread_return((uint32_t)arm_m_cs_ptrs.lr_save)) {
 		return false;
 	}
 
@@ -551,14 +550,14 @@ __asm__(".globl arm_m_exc_exit;"
 	"  bl arm_m_must_switch;"
 	"  ldr r2, =arm_m_cs_ptrs;"
 	"  mov r3, #0;"
-	"  ldr lr, [r2, #8];"    /* lr_save */
+	"  ldr lr, [r2, #8];" /* lr_save */
 	"  cbz r0, 1f;"
 	"  mov lr, #0xfffffffd;" /* integer-only LR */
 	"  ldm r2, {r0, r1};"    /* fields: out, in */
 	"  stm r0, {r4-r11};"    /* out is a switch_frame */
 	"  ldm r1!, {r7-r11};"   /* in is a synth_frame */
 	"  ldm r1, {r4-r6};"
 	"1:\n"
-	"  msr basepri, r3;"     /* release lock taken in must_switch */
+	"  msr basepri, r3;" /* release lock taken in must_switch */
 	"  bx lr;");
 #endif

include/zephyr/arch/arm/arm-m-switch.h

@@ -90,14 +90,14 @@ static inline void arm_m_exc_tail(void)
 	 * our bookeeping around EXC_RETURN, so do it early.
 	 */
 	void z_check_stack_sentinel(void);
-	void *isr_lr = (void *) *arm_m_exc_lr_ptr;
+	void *isr_lr = (void *)*arm_m_exc_lr_ptr;
 
 	if (IS_ENABLED(CONFIG_STACK_SENTINEL)) {
 		z_check_stack_sentinel();
 	}
 	if (isr_lr != arm_m_cs_ptrs.lr_fixup) {
 		arm_m_cs_ptrs.lr_save = isr_lr;
-		*arm_m_exc_lr_ptr = (uint32_t) arm_m_cs_ptrs.lr_fixup;
+		*arm_m_exc_lr_ptr = (uint32_t)arm_m_cs_ptrs.lr_fixup;
 	}
 #endif
 }
@@ -137,92 +137,91 @@ static ALWAYS_INLINE void arm_m_switch(void *switch_to, void **switched_from)
 	 */
 	register uint32_t r4 __asm__("r4") = (uint32_t)switch_to;
 	register uint32_t r5 __asm__("r5") = (uint32_t)switched_from;
-	__asm__ volatile(
-		 _R7_CLOBBER_OPT("push {r7};")
-		/* Construct and push a {r12, lr, pc} group at the top
-		 * of the frame, where PC points to the final restore location
-		 * at the end of this sequence.
-		 */
-		"mov r6, r12;"
-		"mov r7, lr;"
-		"ldr r8, =3f;"    /* address of restore PC */
-		"add r8, r8, #1;" /* set thumb bit */
-		"push {r6-r8};"
-		"sub sp, sp, #24;" /* skip over space for r6-r11 */
-		"push {r0-r5};"
-		"mov r2, #0x01000000;" /* APSR (only care about thumb bit) */
-		"mov r0, #0;"          /* Leave r0 zero for code blow */
+	__asm__ volatile(_R7_CLOBBER_OPT("push {r7};")
+			 /* Construct and push a {r12, lr, pc} group at the top
+			  * of the frame, where PC points to the final restore location
+			  * at the end of this sequence.
+			  */
+			 "mov r6, r12;"
+			 "mov r7, lr;"
+			 "ldr r8, =3f;"    /* address of restore PC */
+			 "add r8, r8, #1;" /* set thumb bit */
+			 "push {r6-r8};"
+			 "sub sp, sp, #24;" /* skip over space for r6-r11 */
+			 "push {r0-r5};"
+			 "mov r2, #0x01000000;" /* APSR (only care about thumb bit) */
+			 "mov r0, #0;"          /* Leave r0 zero for code blow */
 #ifdef CONFIG_BUILTIN_STACK_GUARD
-		"mrs r1, psplim;"
-		"push {r1-r2};"
-		"msr psplim, r0;" /* zero it so we can move the stack */
+			 "mrs r1, psplim;"
+			 "push {r1-r2};"
+			 "msr psplim, r0;" /* zero it so we can move the stack */
 #else
-		"push {r2};"
+			 "push {r2};"
 #endif
 
 #ifdef CONFIG_FPU
-		/* Push FPU state (if active) to our outgoing stack */
-		"   mrs r8, control;" /* read CONTROL.FPCA */
-		"   and r7, r8, #4;"  /* r7 == have_fpu */
-		"   cbz r7, 1f;"
-		"   bic r8, r8, #4;" /* clear CONTROL.FPCA */
-		"   msr control, r8;"
-		"   vmrs r6, fpscr;"
-		"   push {r6};"
-		"   vpush {s0-s31};"
-		"1: push {r7};" /* have_fpu word */
-
-		/* Pop FPU state (if present) from incoming frame in r4 */
-		"   ldm r4!, {r7};" /* have_fpu word */
-		"   cbz r7, 2f;"
-		"   vldm r4!, {s0-s31};" /* (note: sets FPCA bit for us) */
-		"   ldm r4!, {r6};"
-		"   vmsr fpscr, r6;"
-		"2:;"
+			 /* Push FPU state (if active) to our outgoing stack */
+			 "   mrs r8, control;" /* read CONTROL.FPCA */
+			 "   and r7, r8, #4;"  /* r7 == have_fpu */
+			 "   cbz r7, 1f;"
+			 "   bic r8, r8, #4;" /* clear CONTROL.FPCA */
+			 "   msr control, r8;"
+			 "   vmrs r6, fpscr;"
+			 "   push {r6};"
+			 "   vpush {s0-s31};"
+			 "1: push {r7};" /* have_fpu word */
+
+			 /* Pop FPU state (if present) from incoming frame in r4 */
+			 "   ldm r4!, {r7};" /* have_fpu word */
+			 "   cbz r7, 2f;"
+			 "   vldm r4!, {s0-s31};" /* (note: sets FPCA bit for us) */
+			 "   ldm r4!, {r6};"
+			 "   vmsr fpscr, r6;"
+			 "2:;"
 #endif
 
 #if defined(CONFIG_USERSPACE) && defined(CONFIG_USE_SWITCH)
-		"  ldr r8, =arm_m_switch_control;"
-		"  ldr r8, [r8];"
-		"  msr control, r8;"
+			 "  ldr r8, =arm_m_switch_control;"
+			 "  ldr r8, [r8];"
+			 "  msr control, r8;"
 #endif
 
-		/* Save the outgoing switch handle (which is SP), swap stacks,
-		 * and enable interrupts.  The restore process is
-		 * interruptible code (running in the incoming thread) once
-		 * the stack is valid.
-		 */
-		"str sp, [r5];"
-		"mov sp, r4;"
-		"msr basepri, r0;"
+			 /* Save the outgoing switch handle (which is SP), swap stacks,
+			  * and enable interrupts.  The restore process is
+			  * interruptible code (running in the incoming thread) once
+			  * the stack is valid.
+			  */
+			 "str sp, [r5];"
+			 "mov sp, r4;"
+			 "msr basepri, r0;"
 
 	/* Restore is super simple: pop the flags (and stack limit if
 	 * enabled) then slurp in the whole GPR set in two
 	 * instructions. (The instruction encoding disallows popping
 	 * both LR and PC in a single instruction)
 	 */
 #ifdef CONFIG_BUILTIN_STACK_GUARD
-		"pop {r1-r2};"
-		"msr psplim, r1;"
+			 "pop {r1-r2};"
+			 "msr psplim, r1;"
 #else
-		"pop {r2};"
+			 "pop {r2};"
 #endif
 #ifdef _ARM_M_SWITCH_HAVE_DSP
-		"msr apsr_nzcvqg, r2;" /* bonkers syntax */
+			 "msr apsr_nzcvqg, r2;" /* bonkers syntax */
 #else
-		"msr apsr_nzcvq, r2;" /* not even source-compatible! */
+			 "msr apsr_nzcvq, r2;" /* not even source-compatible! */
 #endif
-		"pop {r0-r12, lr};"
-		"pop {pc};"
+			 "pop {r0-r12, lr};"
+			 "pop {pc};"
 
-		"3:" /* Label for restore address */
-		 _R7_CLOBBER_OPT("pop {r7};")
-		::"r"(r4), "r"(r5)
-		 : "r6", "r8", "r9", "r10",
+			 "3:" /* Label for restore address */
+			 _R7_CLOBBER_OPT("pop {r7};")::"r"(r4),
+			 "r"(r5)
+			 : "r6", "r8", "r9", "r10",
 #ifndef CONFIG_ARM_GCC_FP_WORKAROUND
-		    "r7",
+			   "r7",
 #endif
-		    "r11");
+			   "r11");
 }
 
 #ifdef CONFIG_USE_SWITCH