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REFACTOR: Edb cfg operation cutout (#372)
Co-authored-by: ring630 <@gmail.com>
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‎examples/00_edb/use_configuration/import_operations.py‎

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# # Import Ports
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# This example shows how to import operations. In this example, we are going to
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#
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# - Download an example board
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# - Create a configuration file
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# - Add a cutout operation
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# - Import the configuration file
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# ## Import the required packages
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# +
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import json
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from pathlib import Path
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import tempfile
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from ansys.aedt.core.examples.downloads import download_file
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from pyedb import Edb
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AEDT_VERSION = "2025.1"
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NG_MODE = False
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# -
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# Download the example PCB data.
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temp_folder = tempfile.TemporaryDirectory(suffix=".ansys")
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file_edb = download_file(source="edb/ANSYS-HSD_V1.aedb", local_path=temp_folder.name)
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# ## Load example layout and place ports
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edbapp = Edb(file_edb, edbversion=AEDT_VERSION)
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ports = [
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{
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"name": "Port_U1_P",
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"reference_designator": "U1",
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"positive_terminal": {
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"net": "PCIe_Gen4_TX3_CAP_P"
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},
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"negative_terminal": {
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"net": "GND"
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},
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"type": "circuit"
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},
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{
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"name": "Port_U1_N",
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"reference_designator": "U1",
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"positive_terminal": {
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"net": "PCIe_Gen4_TX3_CAP_N"
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},
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"negative_terminal": {
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"net": "GND"
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},
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"type": "circuit"
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},
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{
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"name": "Port_X1_P",
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"reference_designator": "X1",
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"positive_terminal": {
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"net": "PCIe_Gen4_TX3_P"
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},
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"negative_terminal": {
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"net": "GND"
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},
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"type": "circuit"
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},
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{
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"name": "Port_X1_N",
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"reference_designator": "X1",
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"positive_terminal": {
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"net": "PCIe_Gen4_TX3_N"
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},
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"negative_terminal": {
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"net": "GND"
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},
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"type": "circuit"
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}
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]
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cfg_1 = {"ports": ports}
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edbapp.configuration.load(cfg_1)
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edbapp.configuration.run()
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edbapp.save()
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edb_path = edbapp.edbpath
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edbapp.close()
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# ## Cutout by nets
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# Keywords
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#
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# - **reference_list**. List of reference nets.
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# - **Extent_type**. Supported types are `Conforming`, `ConvexHull`, and `Bounding`.
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# - **signal_list**. List of signal nets to keep.
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# - **expansion_size**. Expansion size ratio in meters. The default is ``0.002``.
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# - **use_round_corner**. Whether to use round corners. Defaults to `False`.
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# - **number_of_threads**. Number of threads to use. Defaults to `4`.
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# - **extent_defeature**. Simplifies geometry before applying cutout to aid meshing. Only applies to Conforming bounding box. Defaults to `0` (disabled).
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# - **remove_single_pin_components**. Removes all single-pin RLCs after cutout. Defaults to `False`.
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# - **custom_extent**. List of points defining the custom cutout shape. Overrides the `extent_type` setting.
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# - **custom_extent_units**. Units of the custom extent points. Defaults to `"mm"`. Only valid if `custom_extent` is provided.
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# - **include_partial_instances**. Includes padstacks with bounding boxes intersecting the custom shape. May slow down export. Only valid with `custom_extent` and `use_pyaedt_cutout`.
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# - **keep_voids**. Whether to keep voids intersecting the cutout polygon. Defaults to `True`. Valid only if `custom_extent` is provided.
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# - **check_terminals**. Expands extent to include reference terminals of components with associated models.
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# - **include_pingroups**. Includes terminals of pingroups. Requires `check_terminals` to be `True`.
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# - **expansion_factor**. Computes the maximum between dielectric thickness and trace width (for nets with ports) multiplied by this factor. Defaults to `0` (disabled). Works only with `use_pyaedt_cutout`.
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# - **maximum_iterations**. Maximum number of iterations allowed for cutout search. Defaults to `10`.
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# - **preserve_components_with_model**. Preserves all pins of components with associated models (Spice or NPort). Only applicable for PyAEDT cutouts (excluding point list).
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# - **simple_pad_check**. Uses pad center for intersection detection instead of bounding box. Defaults to `True`. Bounding box method is slower and disables multithreading.
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# - **keep_lines_as_path**. Keeps lines as `Path` instead of converting to `PolygonData`. Only works in Electronics Desktop (3D Layout). May cause issues in SiWave. Defaults to `False`.
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# - **include_voids_in_extents**. Includes voids in the computed extent (for Conforming only). May affect performance. Defaults to `False`.
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cutout = {
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"reference_list": ["GND"],
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"extent_type": "ConvexHull",
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"signal_list": [
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"PCIe_Gen4_TX3_CAP_P",
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"PCIe_Gen4_TX3_CAP_N",
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"PCIe_Gen4_TX3_P",
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"PCIe_Gen4_TX3_N"
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]
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}
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operations = {"cutout": cutout}
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cfg = {"operations": operations}
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# Write configuration into as json file
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file_json = Path(temp_folder.name) / "cutout_1.json"
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with open(file_json, "w") as f:
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json.dump(cfg, f, indent=4, ensure_ascii=False)
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# Apply cutout
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edbapp = Edb(edb_path, edbversion=AEDT_VERSION)
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edbapp.configuration.load(config_file=file_json)
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edbapp.configuration.run()
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edbapp.nets.plot()
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edbapp.close()
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# ## Cutout with auto net identification
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# Keywords
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#
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# - **auto_identify_nets**. Identify nets connected to ports
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# - **enabled**. Resistance threshold. Resistor with value below this threshold is considered as short circuit
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# - **resistor_below**. Resistance threshold. Resistor with value below this threshold is considered as short circuit
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# - **inductor_below**. Inductor threshold. Inductor with value below this threshold is considered as short circuit
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# - **capacitor_above**. Capacitor threshold. Capacitor with value below this threshold is considered as short circuit
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cutout = {
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"auto_identify_nets": {
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"enabled": True,
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"resistor_below": 100,
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"inductor_below": 1,
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"capacitor_above": 1
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},
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"reference_list": ["GND"],
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"extent_type": "ConvexHull"
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}
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operations = {"cutout": cutout}
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cfg = {"operations": operations}
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# Write configuration into as json file
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file_json = Path(temp_folder.name) / "cutout_2.json"
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with open(file_json, "w") as f:
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json.dump(cfg, f, indent=4, ensure_ascii=False)
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# Apply cutout
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edbapp = Edb(edb_path, edbversion=AEDT_VERSION)
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edbapp.configuration.load(config_file=file_json)
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edbapp.configuration.run()
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edbapp.nets.plot()
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edbapp.close()

‎examples/00_edb/use_configuration/index.rst‎

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:doc:`Sources management <import_sources>`
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:doc:`Operations management <import_operations>`
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.. toctree::
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:hidden:
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import_setup_ac
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import_padstack_definitions
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import_components
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import_sources
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import_sources
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import_operations

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