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jvela018pyansys-ci-botgmalinveSamuelopez-ansysSMoraisAnsys
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FIX: Support for Maxwell Transient APhi Solver renaming in 2025R2 (#6414)
Co-authored-by: pyansys-ci-bot <[email protected]> Co-authored-by: Giulia Malinverno <[email protected]> Co-authored-by: Samuel Lopez <[email protected]> Co-authored-by: Samuelopez-ansys <[email protected]> Co-authored-by: Sébastien Morais <[email protected]>
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doc/changelog.d/6414.fixed.md

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
Support for maxwell transient aphi solver renaming in 2025r2

src/ansys/aedt/core/extensions/project/configure_layout.py

Lines changed: 28 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@
2020
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
2121
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
2222
# SOFTWARE.
23-
# Extension template to help get started
23+
2424
from dataclasses import dataclass
2525
import json
2626
import os
@@ -35,7 +35,6 @@
3535

3636
from pyedb import Edb
3737
import toml
38-
import tomli
3938

4039
import ansys.aedt.core
4140
from ansys.aedt.core.examples.downloads import download_file
@@ -45,6 +44,9 @@
4544
from ansys.aedt.core.extensions.misc import get_port
4645
from ansys.aedt.core.extensions.misc import get_process_id
4746
from ansys.aedt.core.extensions.misc import is_student
47+
from ansys.aedt.core.generic.file_utils import read_json
48+
from ansys.aedt.core.generic.file_utils import read_toml
49+
from ansys.aedt.core.generic.file_utils import write_configuration_file
4850
from ansys.aedt.core.generic.settings import settings
4951
from ansys.aedt.core.internal.errors import AEDTRuntimeError
5052

@@ -89,8 +91,7 @@ def __init__(self, data):
8991

9092
def __init__(self, file_path: Union[Path, str]):
9193
self._file_path = Path(file_path)
92-
with open(self._file_path, "rb") as f:
93-
data = tomli.load(f)
94+
data = read_toml(self._file_path)
9495
self.title = data["title"]
9596
self.version = data["version"]
9697
self.layout_file = Path(data["layout_file"])
@@ -101,7 +102,8 @@ def __init__(self, file_path: Union[Path, str]):
101102

102103
supplementary_json = data.get("supplementary_json", "")
103104
if supplementary_json != "":
104-
self.supplementary_json = str(self._file_path.with_name(supplementary_json))
105+
Path(supplementary_json)
106+
self.supplementary_json = str(self._file_path.with_name(Path(supplementary_json).name))
105107
else: # pragma: no cover
106108
self.supplementary_json = ""
107109
self.check()
@@ -265,8 +267,8 @@ def call_back_load(self):
265267

266268
if self.tk_vars.load_overwrite.get():
267269
desktop = ansys.aedt.core.Desktop(
268-
new_desktop_session=False,
269-
specified_version=VERSION,
270+
new_desktop=False,
271+
version=VERSION,
270272
port=PORT,
271273
aedt_process_id=AEDT_PROCESS_ID,
272274
student_version=IS_STUDENT,
@@ -443,32 +445,36 @@ def load_config(config, working_directory, overwrite):
443445

444446
@staticmethod
445447
def export_template_config(working_directory):
448+
export_directory = Path(working_directory)
446449
msg = []
450+
451+
# Read examples serdes
447452
example_master_config = Path(__file__).parent / "resources" / "configure_layout" / "example_serdes.toml"
448-
example_slave_config = (
449-
Path(__file__).parent / "resources" / "configure_layout" / "example_serdes_supplementary.json"
450-
)
451-
export_directory = Path(working_directory)
452-
with open(example_master_config, "r", encoding="utf-8") as file:
453-
content = file.read()
453+
content = read_toml(example_master_config)
454+
content["version"] = VERSION
454455

455-
example_edb = download_file(source="edb/ANSYS_SVP_V1_1.aedb", local_path=working_directory)
456+
# Not download in tests
457+
if "PYTEST_CURRENT_TEST" not in os.environ: # pragma: no cover
458+
example_edb = download_file(source="edb/ANSYS_SVP_V1_1.aedb", local_path=export_directory)
459+
else:
460+
example_edb = export_directory / "ANSYS_SVP_V1_1.aedb"
461+
content["layout_file"] = str(example_edb)
456462

457463
if bool(example_edb):
458464
msg.append(f"Example Edb is downloaded to {example_edb}")
459465
else: # pragma: no cover
460466
msg.append("Failed to download example board.")
461467

462-
with open(export_directory / example_master_config.name, "w", encoding="utf-8") as f:
463-
f.write(content)
464-
msg.append(f"Example master configure file is copied to {export_directory / example_master_config.name}")
468+
example_config = Path(__file__).parent / "resources" / "configure_layout" / "example_serdes_supplementary.json"
469+
example_config_content = read_json(example_config)
470+
example_path = working_directory / "example_serdes_supplementary.json"
471+
write_configuration_file(example_config_content, example_path)
472+
msg.append(f"Example configure file is copied to {export_directory / example_config.name}")
465473

466-
with open(example_slave_config, "r", encoding="utf-8") as file:
467-
content = file.read()
468-
with open(export_directory / example_slave_config.name, "w", encoding="utf-8") as f:
469-
f.write(content)
470-
msg.append(f"Example slave configure file is copied to {export_directory / example_slave_config.name}")
474+
content["supplementary_json"] = str(example_path)
471475

476+
write_configuration_file(content, export_directory / "example_serdes.toml")
477+
msg.append(f"Example master configure file is copied to {export_directory / example_master_config.name}")
472478
return True, "\n\n".join(msg)
473479

474480
@staticmethod

src/ansys/aedt/core/maxwell.py

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -786,6 +786,7 @@ def assign_current(self, assignment, amplitude=1, phase="0deg", solid=True, swap
786786
SolutionsMaxwell3D.ElectricTransient,
787787
SolutionsMaxwell3D.TransientAPhiFormulation,
788788
SolutionsMaxwell3D.ElectroDCConduction,
789+
SolutionsMaxwell3D.TransientAPhi,
789790
):
790791
props["Phase"] = phase
791792
if self.solution_type not in (
@@ -2190,7 +2191,11 @@ def export_element_based_harmonic_force(
21902191
>>> m3d.export_element_based_harmonic_force()
21912192
>>> m3d.release_desktop(True, True)
21922193
"""
2193-
if self.solution_type not in (SolutionsMaxwell3D.Transient, SolutionsMaxwell3D.TransientAPhiFormulation):
2194+
if self.solution_type not in (
2195+
SolutionsMaxwell3D.Transient,
2196+
SolutionsMaxwell3D.TransientAPhi,
2197+
SolutionsMaxwell3D.TransientAPhiFormulation,
2198+
):
21942199
raise AEDTRuntimeError("This methods work only with Maxwell Transient Analysis.")
21952200

21962201
if not output_directory:
@@ -2832,6 +2837,7 @@ def assign_insulating(self, assignment, insulation=None):
28322837
SolutionsMaxwell3D.EddyCurrent,
28332838
SolutionsMaxwell3D.ACMagnetic,
28342839
SolutionsMaxwell3D.Transient,
2840+
SolutionsMaxwell3D.TransientAPhi,
28352841
SolutionsMaxwell3D.TransientAPhiFormulation,
28362842
SolutionsMaxwell3D.DCConduction,
28372843
SolutionsMaxwell3D.ACConduction,
@@ -3639,7 +3645,7 @@ def order_coil_terminals(self, winding_name, list_of_terminals):
36393645
... ]
36403646
>>> app.order_coil_terminals(winding_name=winding, list_of_terminals=updated_connection_order)
36413647
"""
3642-
if self.solution_type != "TransientAPhiFormulation":
3648+
if self.solution_type not in (SolutionsMaxwell3D.TransientAPhi, SolutionsMaxwell3D.TransientAPhiFormulation):
36433649
raise AEDTRuntimeError("Only available in Transient A-Phi Formulation solution type.")
36443650

36453651
self.oboundary.OrderCoilTerminals(["Name:" + winding_name, *list_of_terminals])

src/ansys/aedt/core/modeler/cad/primitives_3d.py

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1776,7 +1776,8 @@ def insert_layout_component(
17761776
"""
17771777
if layout_coordinate_systems is None:
17781778
layout_coordinate_systems = []
1779-
if self._app.solution_type != "Terminal" and self._app.solution_type != "TransientAPhiFormulation":
1779+
if (self._app.solution_type != "Terminal" and
1780+
self._app.solution_type not in ("Transient APhi", "TransientAPhiFormulation")):
17801781
self.logger.warning("Solution type must be terminal in HFSS or APhi in Maxwell")
17811782
return False
17821783

tests/system/extensions/conftest.py

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -113,6 +113,8 @@
113113

114114
logger = pyaedt_logger
115115

116+
os.environ["PYAEDT_SCRIPT_VERSION"] = config["desktopVersion"]
117+
116118

117119
def generate_random_string(length):
118120
characters = string.ascii_letters + string.digits
Binary file not shown.

tests/system/extensions/test_configure_layout.py

Lines changed: 19 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -25,13 +25,26 @@
2525
from pathlib import Path
2626
from unittest.mock import patch
2727

28+
import pytest
2829
import requests
2930

3031
import ansys.aedt.core
3132
from ansys.aedt.core.extensions.project.configure_layout import GUIDE_LINK
3233
from ansys.aedt.core.extensions.project.configure_layout import INTRO_LINK
3334
from ansys.aedt.core.extensions.project.configure_layout import ConfigureLayoutExtension
3435

36+
AEDB_FILE_NAME = "ANSYS_SVP_V1_1"
37+
TEST_SUBFOLDER = "T45"
38+
AEDT_FILE_PATH = Path(__file__).parent / "example_models" / TEST_SUBFOLDER / (AEDB_FILE_NAME + ".aedb")
39+
40+
41+
@pytest.fixture(autouse=True)
42+
def setup_model_in_scratch(local_scratch):
43+
folder = AEDB_FILE_NAME + ".aedb"
44+
target_folder = Path(local_scratch.path) / folder
45+
local_scratch.copyfolder(AEDT_FILE_PATH, target_folder)
46+
return target_folder
47+
3548

3649
def test_links():
3750
for link in [GUIDE_LINK, INTRO_LINK]:
@@ -51,22 +64,24 @@ def test_configure_layout_load(mock_askdirectory, mock_askopenfilename, local_sc
5164
"""Test applying configuration to active design, and saving the new project in a temporary folder."""
5265
test_dir = Path(local_scratch.path)
5366
mock_askdirectory.return_value = str(test_dir)
54-
extension = ConfigureLayoutExtension(withdraw=False)
67+
extension = ConfigureLayoutExtension(withdraw=True)
5568

5669
extension.root.nametowidget("notebook").nametowidget("load").nametowidget("active_design").invoke()
5770
extension.root.nametowidget("notebook").nametowidget("load").nametowidget("generate_template").invoke()
5871
assert (test_dir / "example_serdes.toml").exists()
5972

6073
fpath_config = test_dir / "example_serdes.toml"
74+
6175
mock_askopenfilename.return_value = str(fpath_config)
6276
extension.root.nametowidget("notebook").nametowidget("load").nametowidget("load_config_file").invoke()
6377
assert Path(extension.tabs["Load"].new_aedb).exists()
78+
extension.root.destroy()
6479

6580

6681
@patch("tkinter.filedialog.askdirectory")
6782
def test_configure_layout_export(mock_askdirectory, local_scratch, add_app):
6883
test_dir = Path(local_scratch.path)
69-
extension = ConfigureLayoutExtension(withdraw=False)
84+
extension = ConfigureLayoutExtension(withdraw=True)
7085

7186
add_app("ANSYS-HSD_V1", application=ansys.aedt.core.Hfss3dLayout, subfolder="T45")
7287
mock_askdirectory.return_value = str(test_dir)
@@ -83,7 +98,7 @@ def test_configure_layout_export(mock_askdirectory, local_scratch, add_app):
8398
def test_configure_layout_load_overwrite_active_design(mock_askdirectory, mock_askopenfilename, local_scratch, add_app):
8499
"""Test applying configuration to active design, and overwriting active design."""
85100
test_dir = Path(local_scratch.path)
86-
extension = ConfigureLayoutExtension(withdraw=False)
101+
extension = ConfigureLayoutExtension(withdraw=True)
87102

88103
add_app("ANSYS-HSD_V1", application=ansys.aedt.core.Hfss3dLayout, subfolder="T45")
89104
mock_askdirectory.return_value = str(test_dir)
@@ -102,7 +117,7 @@ def test_configure_layout_batch(mock_askdirectory, local_scratch):
102117

103118
test_dir = Path(local_scratch.path)
104119
mock_askdirectory.return_value = str(test_dir)
105-
extension = ConfigureLayoutExtension(withdraw=False)
120+
extension = ConfigureLayoutExtension(withdraw=True)
106121
extension.root.nametowidget("notebook").nametowidget("load").nametowidget("generate_template").invoke()
107122

108123
main(str(test_dir / "output"), str(Path(test_dir) / "example_serdes.toml"))

tests/system/extensions/test_cutout.py

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -32,13 +32,14 @@
3232
from ansys.aedt.core.extensions.hfss3dlayout.cutout import CutoutData
3333
from ansys.aedt.core.extensions.hfss3dlayout.cutout import main
3434
from ansys.aedt.core.hfss3dlayout import Hfss3dLayout
35+
from tests.system.extensions.conftest import config
3536

3637
AEDB_FILE_NAME = "ANSYS-HSD_V1"
3738
TEST_SUBFOLDER = "T45"
3839
AEDT_FILE_PATH = Path(__file__).parent / "example_models" / TEST_SUBFOLDER / (AEDB_FILE_NAME + ".aedb")
3940

4041

41-
def test_cutout_success(add_app):
42+
def test_cutout_success(add_app, local_scratch):
4243
"""Test the successful execution of the cutout operation in Hfss3dLayout."""
4344

4445
# All DDR4 nets are used as signal nets, GND is used as reference net.
@@ -173,15 +174,18 @@ def test_cutout_success(add_app):
173174
expansion_factor=3.0,
174175
fix_disjoints=True,
175176
)
177+
file_name = AEDB_FILE_NAME + ".aedb"
178+
file_path = Path(local_scratch.path) / file_name
179+
local_scratch.copyfolder(AEDT_FILE_PATH, file_path)
176180

177181
# Check with Edb that nets exist in the original AEDB file.
178-
edb_app = Edb(edbpath=str(AEDT_FILE_PATH))
182+
edb_app = Edb(edbpath=str(file_path), edbversion=config["desktopVersion"])
179183
edb_app_nets = edb_app.nets
180184
assert all(net in edb_app_nets for net in SIGNAL_NETS + REFERENCE_NETS + OTHER_NETS)
181185
edb_app.close_edb()
182186

183187
# Perform the cutout operation.
184-
app = add_app(AEDB_FILE_NAME, application=Hfss3dLayout, subfolder=TEST_SUBFOLDER)
188+
app = add_app(str(file_path), application=Hfss3dLayout, just_open=True)
185189
cutout_path = main(DATA)
186190
app.close_project()
187191

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