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Commit 0726357

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id is replaced by comp_id
1 parent f1f68ff commit 0726357

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+12
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src/ansys/aedt/core/modeler/circuits/primitives_circuit.py

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -359,10 +359,10 @@ def create_interface_port(self, name, location=None, angle=0):
359359
comp_name = self.oeditor.CreateIPort(arg1, arg2)
360360

361361
comp_id = int(comp_name.split(";")[1])
362-
self.add_id_to_component(id, comp_name)
362+
self.add_id_to_component(comp_id, comp_name)
363363
# return id, self.components[id].composed_name
364364
for el in self.components:
365-
if ("IPort@" + name + ";" + str(id)) in self.components[el].composed_name:
365+
if ("IPort@" + name + ";" + str(comp_id)) in self.components[el].composed_name:
366366
return self._app.design_excitations[name]
367367
return False
368368

@@ -413,9 +413,9 @@ def create_page_port(self, name, location=None, angle=0, label_position="Auto"):
413413
],
414414
)
415415

416-
id = int(comp_name.split(";")[1])
416+
comp_id = int(comp_name.split(";")[1])
417417
# self.refresh_all_ids()
418-
self.add_id_to_component(id, comp_name)
418+
self.add_id_to_component(comp_id, comp_name)
419419
if label_position == "Auto":
420420
if angle == 270:
421421
new_loc = "Top"
@@ -432,7 +432,7 @@ def create_page_port(self, name, location=None, angle=0, label_position="Auto"):
432432
"NAME:PropDisplayPropTab",
433433
[
434434
"NAME:PropServers",
435-
self.components[id].composed_name,
435+
self.components[comp_id].composed_name,
436436
],
437437
[
438438
"NAME:ChangedProps",
@@ -441,7 +441,7 @@ def create_page_port(self, name, location=None, angle=0, label_position="Auto"):
441441
],
442442
]
443443
)
444-
return self.components[id]
444+
return self.components[comp_id]
445445

446446
@pyaedt_function_handler()
447447
def create_gnd(self, location=None, angle=0, page=1):
@@ -476,7 +476,7 @@ def create_gnd(self, location=None, angle=0, page=1):
476476
["NAME:Attributes", "Page:=", page, "X:=", xpos, "Y:=", ypos, "Angle:=", angle, "Flip:=", False],
477477
)
478478
comp_id = int(name.split(";")[1])
479-
self.add_id_to_component(id, name)
479+
self.add_id_to_component(comp_id, name)
480480
# return id, self.components[id].composed_name
481481
for el in self.components:
482482
if name in self.components[el].composed_name:
@@ -1405,7 +1405,7 @@ def add_id_to_component(self, comp_id, name=None):
14051405
"""
14061406
if name:
14071407
name = name.split(";")
1408-
if len(name) > 1 and str(id) == name[1]:
1408+
if len(name) > 1 and str(comp_id) == name[1]:
14091409
o = CircuitComponent(self, tabname=self.tab_name)
14101410
o.name = name[0]
14111411
if len(name) > 2:
@@ -1714,10 +1714,10 @@ def _index_components(self, library_path=None):
17141714
for compname, comp_value in comps.items():
17151715
root_name = str(Path(file).with_suffix(""))
17161716
full_path = list(Path(root_name).parts)
1717-
id = full_path.index(root) + 1
1718-
if self._component_manager.design_libray in full_path[id:]:
1719-
id += 1
1720-
comp_lib = "\\".join(full_path[id:]) + ":" + compname
1717+
comp_id = full_path.index(root) + 1
1718+
if self._component_manager.design_libray in full_path[comp_id:]:
1719+
comp_id += 1
1720+
comp_lib = "\\".join(full_path[comp_id:]) + ":" + compname
17211721
self.components[comp_lib] = ComponentInfo(
17221722
compname, self._component_manager, file, comp_lib.split(":")[0]
17231723
)

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