diff --git a/doc/changelog.d/6775.fixed.md b/doc/changelog.d/6775.fixed.md new file mode 100644 index 00000000000..ee8e54facc9 --- /dev/null +++ b/doc/changelog.d/6775.fixed.md @@ -0,0 +1 @@ +Bug located in primitives circuit module diff --git a/src/ansys/aedt/core/modeler/circuits/primitives_circuit.py b/src/ansys/aedt/core/modeler/circuits/primitives_circuit.py index 588353791f4..ee51be68070 100644 --- a/src/ansys/aedt/core/modeler/circuits/primitives_circuit.py +++ b/src/ansys/aedt/core/modeler/circuits/primitives_circuit.py @@ -1387,7 +1387,7 @@ def refresh_all_ids(self): o.schematic_id = int(name[1].split(":")[0]) objID = int(o.schematic_id) else: - o.id = int(name[1]) + o.id = name[1] o.schematic_id = name[2] objID = int(o.schematic_id) @@ -1424,7 +1424,7 @@ def add_id_to_component(self, component_id, name=None): o = CircuitComponent(self, tabname=self.tab_name) o.name = name[0] if len(name) > 2: - o.id = int(name[1]) + o.id = name[1] o.schematic_id = int(name[2]) objID = o.schematic_id else: @@ -1448,7 +1448,7 @@ def add_id_to_component(self, component_id, name=None): o = CircuitComponent(self, tabname=self.tab_name) o.name = name[0] if len(name) > 2: - o.id = int(name[1]) + o.id = name[1] o.schematic_id = int(name[2]) objID = o.schematic_id else: diff --git a/src/ansys/aedt/core/modeler/circuits/primitives_nexxim.py b/src/ansys/aedt/core/modeler/circuits/primitives_nexxim.py index 0261ed2caa9..afcfe6c431e 100644 --- a/src/ansys/aedt/core/modeler/circuits/primitives_nexxim.py +++ b/src/ansys/aedt/core/modeler/circuits/primitives_nexxim.py @@ -225,7 +225,7 @@ def create_subcircuit(self, location=None, angle=None, name=None, nested_subcirc name = match[0].split(";") o.name = name[0] o.schematic_id = int(name[2]) - o.id = int(name[1]) + o.id = name[1] return o self.refresh_all_ids() for el in self.components: diff --git a/tests/system/general/test_21_Circuit.py b/tests/system/general/test_21_Circuit.py index a7c2e2c223d..3a94f3afbe1 100644 --- a/tests/system/general/test_21_Circuit.py +++ b/tests/system/general/test_21_Circuit.py @@ -96,18 +96,18 @@ def init(self, examples): def test_01a_create_inductor(self, aedtapp): myind = aedtapp.modeler.schematic.create_inductor(value=1e-9, location=[1000, 1000]) - assert type(myind.id) is int + assert type(myind.id) is str assert myind.parameters["L"] == "1e-09" def test_02_create_resistor(self, aedtapp): myres = aedtapp.modeler.schematic.create_resistor(value=50, location=[2000, 1000]) assert myres.refdes != "" - assert type(myres.id) is int + assert type(myres.id) is str assert myres.parameters["R"] == "50" def test_03_create_capacitor(self, aedtapp): mycap = aedtapp.modeler.schematic.create_capacitor(value=1e-12, location=[1000, 2000]) - assert type(mycap.id) is int + assert type(mycap.id) is str assert mycap.parameters["C"] == "1e-12" tol = 1e-12 assert abs(mycap.pins[0].location[1] - 2000) < tol @@ -116,7 +116,7 @@ def test_03_create_capacitor(self, aedtapp): def test_04_getpin_names(self, aedtapp): mycap2 = aedtapp.modeler.schematic.create_capacitor(value=1e-12) pinnames = aedtapp.modeler.schematic.get_pins(mycap2) - pinnames2 = aedtapp.modeler.schematic.get_pins(mycap2.id) + pinnames2 = aedtapp.modeler.schematic.get_pins(int(mycap2.id)) pinnames3 = aedtapp.modeler.schematic.get_pins(mycap2.composed_name) assert pinnames2 == pinnames3 assert type(pinnames) is list @@ -460,7 +460,7 @@ def test_29a_create_circuit_from_spice_edit_symbol(self, aedtapp): def test_30_create_subcircuit(self, aedtapp): subcircuit = aedtapp.modeler.schematic.create_subcircuit(location=[0.0, 0.0], angle=0) assert type(subcircuit.location) is list - assert type(subcircuit.id) is int + assert type(subcircuit.id) is str assert subcircuit.component_info assert subcircuit.location[0] == 0.0 assert subcircuit.location[1] == 0.0 @@ -476,7 +476,7 @@ def test_31_duplicate(self, aedtapp): # pragma: no cover new_subcircuit = aedtapp.modeler.schematic.duplicate(subcircuit.composed_name, location=[0.0508, 0.0], angle=0) assert type(new_subcircuit.location) is list - assert type(new_subcircuit.id) is int + assert type(new_subcircuit.id) is str assert new_subcircuit.location[0] == 0.04826 assert new_subcircuit.location[1] == -0.00254 assert new_subcircuit.angle == 0.0 @@ -547,7 +547,7 @@ def test_35_netlist_data_block(self, aedtapp, local_scratch): def test_36_create_voltage_probe(self, aedtapp): myprobe = aedtapp.modeler.components.create_voltage_probe(name="voltage_probe") - assert type(myprobe.id) is int + assert type(myprobe.id) is str def test_37_draw_graphical_primitives(self, aedtapp): line = aedtapp.modeler.components.create_line([[0, 0], [1, 1]]) @@ -877,7 +877,7 @@ def test_46_create_vpwl(self, aedtapp): # default inputs myres = aedtapp.modeler.schematic.create_voltage_pwl(name="V1") assert myres.refdes != "" - assert type(myres.id) is int + assert type(myres.id) is str assert myres.parameters["time1"] == "0s" assert myres.parameters["time2"] == "0s" assert myres.parameters["val1"] == "0V" @@ -885,7 +885,7 @@ def test_46_create_vpwl(self, aedtapp): # time and voltage input list myres = aedtapp.modeler.schematic.create_voltage_pwl(name="V2", time_list=[0, "1u"], voltage_list=[0, 1]) assert myres.refdes != "" - assert type(myres.id) is int + assert type(myres.id) is str assert myres.parameters["time1"] == "0" assert myres.parameters["time2"] == "1u" assert myres.parameters["val1"] == "0" @@ -1043,10 +1043,10 @@ def test_51_import_asc(self, aedtapp): def test_52_create_current_probe(self, aedtapp): iprobe = aedtapp.modeler.schematic.create_current_probe(name="test_probe", location=[0.4, 0.2]) - assert type(iprobe.id) is int + assert type(iprobe.id) is str assert iprobe.InstanceName == "test_probe" iprobe2 = aedtapp.modeler.schematic.create_current_probe(location=[0.8, 0.2]) - assert type(iprobe2.id) is int + assert type(iprobe2.id) is str def test_53_import_table(self, aedtapp): file_header = Path(TESTS_GENERAL_PATH) / "example_models" / test_subfolder / "table_header.csv" diff --git a/tests/system/general/test_22_Circuit_DynamicLink.py b/tests/system/general/test_22_Circuit_DynamicLink.py index 3a869551dfc..c90951b3969 100644 --- a/tests/system/general/test_22_Circuit_DynamicLink.py +++ b/tests/system/general/test_22_Circuit_DynamicLink.py @@ -109,13 +109,13 @@ def test_pin_names(self, aedtapp, local_scratch): def test_02_add_subcircuits_3dlayout(self, aedtapp): layout_design = "layout_cutout" hfss3Dlayout_comp = aedtapp.modeler.schematic.add_subcircuit_3dlayout(layout_design) - assert hfss3Dlayout_comp.id == 86 + assert hfss3Dlayout_comp.id == "86" assert hfss3Dlayout_comp @pytest.mark.skipif(config["NonGraphical"] and is_linux, reason="Method not working in Linux and Non graphical.") def test_03_add_subcircuits_hfss_link(self, uusb, aedtapp): hfss_comp = aedtapp.modeler.schematic.add_subcircuit_dynamic_link(uusb, comp_name="uUSB") - assert hfss_comp.id == 86 + assert hfss_comp.id == "86" assert aedtapp.modeler.schematic.refresh_dynamic_link("uUSB") @pytest.mark.skipif(config["NonGraphical"] and is_linux, reason="Method not working in Linux and Non graphical") diff --git a/tests/system/solvers/test_00_analyze.py b/tests/system/solvers/test_00_analyze.py index 0778b70e5a4..c03f841c545 100644 --- a/tests/system/solvers/test_00_analyze.py +++ b/tests/system/solvers/test_00_analyze.py @@ -497,7 +497,7 @@ def test_circuit_add_3dlayout_component(self, circuit_app): setup = circuit_app.create_setup("test_06b_LNA") setup.add_sweep_step(start=0, stop=5, step_size=0.01) myedb = circuit_app.modeler.schematic.add_subcircuit_3dlayout("main") - assert type(myedb.id) is int + assert type(myedb.id) is str ports = myedb.pins tx = ports rx = ports