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Add simple_alu design with test
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
1 parent 73b15a2 commit bc29061

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10 files changed

+680
-42
lines changed

10 files changed

+680
-42
lines changed

‎bench/run.py‎

Lines changed: 44 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@ class TestAlwaysAssign(unittest.TestCase):
7070
RESULTS_DIR = f"{BASE_DIR}/results/{PLATFORM}/{DESIGN_NAME}"
7171
MAIN_SRC = f"{RESULTS_DIR}/base/1_synth.v"
7272
TEST_BENCH = f"{ORFS_ROOT}/bench/{DESIGN_NAME}/test_bench_top.v"
73-
AES_SRC = f"{BASE_DIR}/designs/src/{DESIGN_NAME}"
73+
DESIGN_SRC = f"{BASE_DIR}/designs/src/{DESIGN_NAME}"
7474
FILES = f"{SRCS} {MAIN_SRC} {TEST_BENCH}"
7575

7676
@classmethod
@@ -83,7 +83,7 @@ def setUpClass(self):
8383
def test_verilator(self):
8484
self.assertFalse(
8585
subprocess.call(
86-
f"{VERILATOR_ROOT}/bin/verilator -Mdir {self.RESULTS_DIR}/verilator --binary --error-limit 9999999 -Wno-MULTIDRIVEN -Wno-NOLATCH {self.FILES} +incdir+{self.AES_SRC} -j {CPUS} --build-jobs {CPUS}",
86+
f"{VERILATOR_ROOT}/bin/verilator -Mdir {self.RESULTS_DIR}/verilator --binary --error-limit 9999999 -Wno-MULTIDRIVEN -Wno-NOLATCH {self.FILES} +incdir+{self.DESIGN_SRC} -j {CPUS} --build-jobs {CPUS}",
8787
shell=True))
8888
self.assertFalse(
8989
subprocess.call(
@@ -94,7 +94,48 @@ def test_verilator(self):
9494
"Requires QUESTA_BIN and LM_LICENSE_FILE defined")
9595
def test_questa(self):
9696
subprocess.call(
97-
f"{QUESTA_BIN} {self.FILES} +incdir+{self.AES_SRC} -outdir {self.RESULTS_DIR}/questa",
97+
f"{QUESTA_BIN} {self.FILES} +incdir+{self.DESIGN_SRC} -outdir {self.RESULTS_DIR}/questa",
98+
shell=True,
99+
env=dict(os.environ, LM_LICENSE_FILE=LM_LICENSE_FILE))
100+
101+
@classmethod
102+
def tearDownClass(self):
103+
subprocess.call(
104+
f"make -C {ORFS_ROOT}/flow DESIGN_CONFIG={self.DESIGN_CONFIG} clean_synth",
105+
shell=True)
106+
107+
108+
class TestSimpleAlu(unittest.TestCase):
109+
DESIGN_NAME = "simple_alu"
110+
DESIGN_CONFIG = f"designs/{PLATFORM}/{DESIGN_NAME}/config.mk"
111+
RESULTS_DIR = f"{BASE_DIR}/results/{PLATFORM}/{DESIGN_NAME}"
112+
MAIN_SRC = f"{RESULTS_DIR}/base/1_synth.v"
113+
TEST_BENCH = f"{ORFS_ROOT}/bench/{DESIGN_NAME}/test_bench_top.v"
114+
DESIGN_SRC = f"{BASE_DIR}/designs/src/{DESIGN_NAME}"
115+
FILES = f"{SRCS} {MAIN_SRC} {TEST_BENCH}"
116+
117+
@classmethod
118+
def setUpClass(self):
119+
subprocess.call(
120+
f"make -C {ORFS_ROOT}/flow DESIGN_CONFIG={self.DESIGN_CONFIG} synth",
121+
shell=True)
122+
123+
@unittest.skipIf(VERILATOR_ROOT is None, "Requires VERILATOR_ROOT defined")
124+
def test_verilator(self):
125+
self.assertFalse(
126+
subprocess.call(
127+
f"{VERILATOR_ROOT}/bin/verilator -Mdir {self.RESULTS_DIR}/verilator --binary --error-limit 9999999 -Wno-MULTIDRIVEN -Wno-NOLATCH {self.FILES} +incdir+{self.DESIGN_SRC} -j {CPUS} --build-jobs {CPUS}",
128+
shell=True))
129+
self.assertFalse(
130+
subprocess.call(
131+
f"{self.RESULTS_DIR}/verilator/Vasap7sc7p5t_AO_RVT_TT_201020",
132+
shell=True))
133+
134+
@unittest.skipIf(QUESTA_BIN is None or LM_LICENSE_FILE is None,
135+
"Requires QUESTA_BIN and LM_LICENSE_FILE defined")
136+
def test_questa(self):
137+
subprocess.call(
138+
f"{QUESTA_BIN} {self.FILES} +incdir+{self.DESIGN_SRC} -outdir {self.RESULTS_DIR}/questa",
98139
shell=True,
99140
env=dict(os.environ, LM_LICENSE_FILE=LM_LICENSE_FILE))
100141

‎bench/simple_alu/test_bench_top.v‎

Lines changed: 43 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,43 @@
1+
`timescale 1 ns / 1 ns
2+
module tb;
3+
reg clk = 0;
4+
reg[7:0] a = 0;
5+
reg[7:0] b = 0;
6+
reg[1:0] op;
7+
wire[7:0] out;
8+
simple_alu uut(.*);
9+
10+
always #1 clk = ~clk;
11+
initial begin
12+
#50
13+
a = 42;
14+
b = 99;
15+
op = 0 /*ADD*/;
16+
#50
17+
if (out != 42 + 99) $stop;
18+
$display("a=%0d, b=%0d, op=%0d, out=%0d", a, b, op, out);
19+
20+
a = 99;
21+
b = 42;
22+
op = 1 /*SUB*/;
23+
#50
24+
if (out != 99 - 42) $stop;
25+
$display("a=%0d, b=%0d, op=%0d, out=%0d", a, b, op, out);
26+
27+
a = 1;
28+
b = 0;
29+
op = 2 /*AND*/;
30+
#50
31+
if (out != 0) $stop;
32+
$display("a=%0d, b=%0d, op=%0d, out=%0d", a, b, op, out);
33+
34+
a = 1;
35+
b = 0;
36+
op = 3 /*OR*/;
37+
#50
38+
if (out != 1) $stop;
39+
$display("a=%0d, b=%0d, op=%0d, out=%0d", a, b, op, out);
40+
end
41+
42+
initial #10000 $finish;
43+
endmodule

‎flow/designs/asap7/simple_alu/autotuner.json‎

Lines changed: 92 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,92 @@
1+
{
2+
"_SDC_FILE_PATH": "constraint.sdc",
3+
"_SDC_CLK_PERIOD": {
4+
"type": "float",
5+
"minmax": [
6+
300,
7+
600
8+
],
9+
"step": 0
10+
},
11+
"CORE_UTILIZATION": {
12+
"type": "int",
13+
"minmax": [
14+
0,
15+
5
16+
],
17+
"step": 1
18+
},
19+
"CORE_ASPECT_RATIO": {
20+
"type": "float",
21+
"minmax": [
22+
0.9,
23+
1.1
24+
],
25+
"step": 0
26+
},
27+
"CORE_MARGIN": {
28+
"type": "int",
29+
"minmax": [
30+
2,
31+
2
32+
],
33+
"step": 0
34+
},
35+
"CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": {
36+
"type": "int",
37+
"minmax": [
38+
0,
39+
3
40+
],
41+
"step": 1
42+
},
43+
"CELL_PAD_IN_SITES_DETAIL_PLACEMENT": {
44+
"type": "int",
45+
"minmax": [
46+
0,
47+
3
48+
],
49+
"step": 1
50+
},
51+
"_FR_LAYER_ADJUST": {
52+
"type": "float",
53+
"minmax": [
54+
0.0,
55+
0.1
56+
],
57+
"step": 0
58+
},
59+
"PLACE_DENSITY_LB_ADDON": {
60+
"type": "float",
61+
"minmax": [
62+
0.0,
63+
0.2
64+
],
65+
"step": 0
66+
},
67+
"_PINS_DISTANCE": {
68+
"type": "int",
69+
"minmax": [
70+
1,
71+
1
72+
],
73+
"step": 1
74+
},
75+
"CTS_CLUSTER_SIZE": {
76+
"type": "int",
77+
"minmax": [
78+
10,
79+
200
80+
],
81+
"step": 1
82+
},
83+
"CTS_CLUSTER_DIAMETER": {
84+
"type": "int",
85+
"minmax": [
86+
20,
87+
400
88+
],
89+
"step": 1
90+
},
91+
"_FR_FILE_PATH": ""
92+
}

‎flow/designs/asap7/simple_alu/config.mk‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
export PLATFORM = asap7
2+
3+
export DESIGN_NAME = simple_alu
4+
export DESIGN_NICKNAME = simple_alu
5+
6+
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.sv
7+
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
8+
9+
export ABC_AREA = 1
10+
11+
export CORE_UTILIZATION = 40
12+
export CORE_ASPECT_RATIO = 1
13+
export CORE_MARGIN = 2
14+
export PLACE_DENSITY = 0.65
15+
export TNS_END_PERCENT = 100
16+
export EQUIVALENCE_CHECK ?= 1
17+
export REMOVE_CELLS_FOR_EQY = TAPCELL*

‎flow/designs/asap7/simple_alu/constraint.sdc‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,13 @@
1+
set clk_name clk
2+
set clk_port_name clk
3+
set clk_period 400
4+
set clk_io_pct 0.2
5+
6+
set clk_port [get_ports $clk_port_name]
7+
8+
create_clock -name $clk_name -period $clk_period $clk_port
9+
10+
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
11+
12+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
13+
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

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