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1 parent c4c394c commit 6ea9579Copy full SHA for 6ea9579
synthesis/build_defs.bzl
@@ -363,6 +363,11 @@ synthesize_rtl = rule(
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"deps": attr.label_list(
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providers = [[VerilogInfo], [UhdmInfo]],
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),
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+ "early_techmap": attr.label(
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+ allow_single_file = True,
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+ doc = "verilog/system verilog file for early techmap process",
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+ mandatory = False,
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+ ),
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"extra_tcl_command": attr.string(
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default = "",
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@@ -399,11 +404,6 @@ synthesize_rtl = rule(
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executable = True,
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cfg = "exec",
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- "early_techmap": attr.label(
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- allow_single_file = True,
- mandatory = False,
- doc = "verilog/system verilog file for early techmap process"
- ),
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},
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)
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