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| 1 | +// Following registers are currently not handled |
| 2 | +// Tied to '0 |
| 3 | +-node *.hwif_in.I3CBase.CONTROLLER_DEVICE_ADDR.DYNAMIC_ADDR_VALID* |
| 4 | +-node *.hwif_in.I3CBase.CONTROLLER_DEVICE_ADDR.DYNAMIC_ADDR* |
| 5 | +-node *.hwif_in.I3CBase.HC_CONTROL.RESUME* |
| 6 | +-node *.hwif_in.I3CBase.HC_CONTROL.BUS_ENABLE.* |
| 7 | +-node *.hwif_in.I3CBase.RESET_CONTROL.SOFT_RST.* |
| 8 | +-node *.hwif_in.I3CBase.PRESENT_STATE.* |
| 9 | +-node *.hwif_in.I3CBase.INTR_STATUS.* |
| 10 | +-node *.hwif_in.I3CBase.DCT_SECTION_OFFSET.* |
| 11 | +-node *.hwif_in.I3CBase.IBI_DATA_ABORT_CTRL.* |
| 12 | +-node *.hwif_in.PIOControl.PIO_INTR_STATUS.* |
| 13 | +-node *.hwif_in.I3C_EC.CtrlCfg.CONTROLLER_CONFIG.* |
| 14 | +-node *.hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_VIRT_DEVICE_ADDR.VIRT_STATIC_ADDR* |
| 15 | +-node *.hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_STATUS* |
| 16 | +-node *.hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE* |
| 17 | +-node *.hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_GETCAPS* |
| 18 | +-node *.hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RST_ACTION* |
| 19 | +-node *.hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_TIME_PERIPHERAL* |
| 20 | +-node *.hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_TIME_TARGET* |
| 21 | +-node *.hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_DYNAMIC_ADDR* |
| 22 | +-node *.hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE* |
| 23 | +-node *.hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS* |
| 24 | +-node *.hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL.* |
| 25 | +-node *.hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_ADDR.STATIC_ADDR* |
| 26 | +-node *.hwif_in.I3C_EC.TTI.INTERRUPT_STATUS.IBI_THLD_STAT.* |
| 27 | +-node *.hwif_in.I3C_EC.TTI.INTERRUPT_STATUS.TRANSFER_ERR_STAT.* |
| 28 | +-node *.hwif_in.I3C_EC.TTI.INTERRUPT_STATUS.TRANSFER_ABORT_STAT.* |
| 29 | +-node *.hwif_in.I3C_EC.TTI.INTERRUPT_STATUS.TX_DESC_THLD_STAT.* |
| 30 | +-node *.hwif_in.I3C_EC.TTI.INTERRUPT_STATUS.TX_DATA_THLD_STAT.* |
| 31 | +-node *.hwif_in.I3C_EC.TTI.INTERRUPT_STATUS.TX_DESC_TIMEOUT.* |
| 32 | +-node *.hwif_in.I3C_EC.TTI.INTERRUPT_STATUS.RX_DESC_TIMEOUT.* |
| 33 | +-node *.hwif_in.I3C_EC.TTI.INTERRUPT_STATUS.PENDING_INTERRUPT.* |
| 34 | +-node *.hwif_in.I3C_EC.TTI.QUEUE_THLD_CTRL.IBI_THLD.* |
| 35 | +-node *.hwif_in.I3C_EC.TTI.RESET_CONTROL.SOFT_RST.* |
| 36 | + |
| 37 | +// Read-only by both SW & HW, tied to const |
| 38 | +-node *.hwif_out.I3C_EC.TERMINATION_EXTCAP_HEADER.* |
| 39 | +-node *.hwif_out.I3C_EC.SoCMgmtIf.EXTCAP_HEADER.* |
| 40 | +-node *.hwif_out.I3C_EC.CtrlCfg.EXTCAP_HEADER.* |
| 41 | +-node *.hwif_out.I3C_EC.TTI.QUEUE_SIZE.* |
| 42 | +-node *.hwif_out.I3C_EC.StdbyCtrlMode.EXTCAP_HEADER* |
| 43 | +-node *.hwif_out.I3C_EC.StdbyCtrlMode.STBY_CR_CAPABILITIES.SIMPLE_CRR_SUPPORT* |
| 44 | +-node *.hwif_out.I3C_EC.StdbyCtrlMode.STBY_CR_CAPABILITIES.TARGET_XACT_SUPPORT* |
| 45 | +-node *.hwif_out.I3C_EC.StdbyCtrlMode.STBY_CR_CAPABILITIES.DAA_SETAASA_SUPPORT* |
| 46 | +-node *.hwif_out.I3C_EC.StdbyCtrlMode.STBY_CR_CAPABILITIES.DAA_SETDASA_SUPPORT* |
| 47 | +-node *.hwif_out.I3C_EC.StdbyCtrlMode.STBY_CR_CAPABILITIES.DAA_ENTDAA_SUPPORT* |
| 48 | + |
| 49 | +// Reserved |
| 50 | +-node *.DEVICE_ID_RESERVED* |
| 51 | +-node *.HW_STATUS.RESERVED_7_3* |
| 52 | +-node *.INDIRECT_FIFO_RESERVED* |
| 53 | +-node *.SOC_MGMT_RSVD* |
| 54 | +-node *.__rsvd* |
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