@@ -122,9 +122,9 @@ module i3c_target_fsm #(
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output logic parity_err_o,
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output logic rx_overflow_err_o,
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- output logic virtual_device_tx_o ,
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- input logic virtual_device_tx_done_i ,
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- input logic recovery_mode_i ,
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+ output logic virtual_device_sel_o ,
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+ input logic virtual_device_rdy_i ,
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+ output logic xfer_in_progress_o ,
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output logic tx_pr_start_o,
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output logic tx_pr_abort_o
@@ -235,13 +235,15 @@ module i3c_target_fsm #(
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logic bus_rnw_d, bus_rnw_q;
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logic [6 : 0 ] bus_addr_d, bus_addr_q;
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logic is_our_addr_match, is_rsvd_byte_match, is_virtual_addr_match;
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- assign is_our_addr_match = recovery_mode_i ? 1'b0 :
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- target_dyn_address_valid_i ? (target_dyn_address_i == bus_addr_q) :
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+
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+ assign is_our_addr_match = target_dyn_address_valid_i ? (target_dyn_address_i == bus_addr_q) :
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target_sta_address_valid_i ? (target_sta_address_i == bus_addr_q) :
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1'b0 ;
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+
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assign is_virtual_addr_match = virtual_target_dyn_address_valid_i ? (virtual_target_dyn_address_i == bus_addr_q) :
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- virtual_target_sta_address_valid_i ? (virtual_target_sta_address_i == bus_addr_q) :
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- 1'b0 ;
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+ virtual_target_sta_address_valid_i ? (virtual_target_sta_address_i == bus_addr_q) :
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+ 1'b0 ;
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+
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assign is_rsvd_byte_match = ({ bus_addr_q, bus_rnw_q} == 8'hFC );
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always_ff @ (posedge clk_i or negedge rst_ni) begin : update_bus_addr_matcher
@@ -580,15 +582,36 @@ module i3c_target_fsm #(
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assign target_idle_o = (state_q == Idle);
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- always_ff @ (posedge clk_i or negedge rst_ni) begin : virtual_device_tx_latch
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+ always_ff @ (posedge clk_i or negedge rst_ni) begin : virtual_device_sel_latch
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if (! rst_ni) begin
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- virtual_device_tx_o <= 1'b0 ;
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- end else begin
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- if ((state_q == TxAckSByte) && is_virtual_addr_match) begin
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- virtual_device_tx_o <= 1'b1 ;
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- end else if (state_q == Idle) virtual_device_tx_o <= 1'b0 ;
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- end
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+ virtual_device_sel_o <= '0 ;
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+ end else unique case (state_q)
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+ CheckFByte:
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+ if (! is_rsvd_byte_match && virtual_device_sel_o != is_virtual_addr_match)
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+ virtual_device_sel_o <= is_virtual_addr_match;
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+ CheckSByte:
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+ if (! is_rsvd_byte_match && virtual_device_sel_o != is_virtual_addr_match)
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+ virtual_device_sel_o <= is_virtual_addr_match;
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+ default :
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+ virtual_device_sel_o <= virtual_device_sel_o;
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+ endcase
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end
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+
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+ always_ff @ (posedge clk_i or negedge rst_ni) begin
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+ if (! rst_ni) begin
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+ xfer_in_progress_o <= '0 ;
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+ end else unique case (state_q)
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+ Idle:
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+ xfer_in_progress_o <= '0 ;
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+ CheckFByte:
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+ xfer_in_progress_o <= (is_our_addr_match || is_virtual_addr_match);
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+ CheckSByte:
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+ xfer_in_progress_o <= (is_our_addr_match || is_virtual_addr_match);
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+ default :
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+ xfer_in_progress_o <= xfer_in_progress_o;
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+ endcase
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+ end
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+
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// TODO: Also sub FSM should contribute
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// TODO: Maybe we can do it based on write module rather than states
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assign target_transmitting_o =
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