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Use I3C_ASSERT instead of CALIPTRA
Signed-off-by: Karol Gugala <[email protected]>
1 parent f587bd0 commit 22785d0

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7 files changed

+82
-15
lines changed

7 files changed

+82
-15
lines changed

‎src/csr/I3CCSR.sv‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
22
// https://github.com/SystemRDL/PeakRDL-regblock
33

4-
`include "caliptra_sva.svh"
4+
`include "i3c_sva.svh"
55

66
module I3CCSR (
77
input wire clk,
@@ -10386,6 +10386,6 @@ module I3CCSR (
1038610386
assign cpuif_rd_data = readback_data;
1038710387
assign cpuif_rd_err = readback_err;
1038810388

10389-
`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, !hwif_in.rst_ni)
10389+
`I3C_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, !hwif_in.rst_ni)
1039010390

1039110391
endmodule

‎src/ctrl/i2c_controller_fsm.sv‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,8 @@
44
//
55
// Description: I2C finite state machine
66

7+
`include "i3c_sva.svh"
8+
79
module i2c_controller_fsm
810
import controller_pkg::*;
911
#(
@@ -938,7 +940,7 @@ module i2c_controller_fsm
938940
(stretch_idle_cnt[30:0] > stretch_timeout_i) && timeout_enable_i;
939941

940942
// Make sure we never attempt to send a single cycle glitch
941-
`CALIPTRA_ASSERT(SclOutputGlitch_A, $rose(scl_o) |-> ##1 scl_o)
943+
`I3C_ASSERT(SclOutputGlitch_A, $rose(scl_o) |-> ##1 scl_o)
942944

943945
// TODO: Handle the assertion below
944946
// // I2C bus outputs

‎src/i3c.f‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
+incdir+${CALIPTRA_ROOT}/src/libs/rtl
22
+incdir+${CALIPTRA_ROOT}/src/caliptra_prim/rtl
33
+incdir+${I3C_ROOT_DIR}/src
4+
+incdir+${I3C_ROOT_DIR}/src/libs
45
+incdir+${I3C_ROOT_DIR}/src/libs/axi
56
${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_pkg.sv
67
${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv

‎src/libs/i3c_sva.svh‎

Lines changed: 61 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,61 @@
1+
// SPDX-License-Identifier: Apache-2.0
2+
//
3+
// Licensed under the Apache License, Version 2.0 (the "License");
4+
// you may not use this file except in compliance with the License.
5+
// You may obtain a copy of the License at
6+
//
7+
// http://www.apache.org/licenses/LICENSE-2.0
8+
//
9+
// Unless required by applicable law or agreed to in writing, software
10+
// distributed under the License is distributed on an "AS IS" BASIS,
11+
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12+
// See the License for the specific language governing permissions and
13+
// limitations under the License.
14+
15+
`ifndef I3C_SVA
16+
`define I3C_SVA
17+
18+
// Default clk and reset signals used by assertion macros below.
19+
`define I3C_ASSERT_DEFAULT_CLK clk_i
20+
`define I3C_ASSERT_DEFAULT_RST !rst_ni
21+
22+
// Converts an arbitrary block of code into a Verilog string
23+
`define STRINGIFY(__x) `"__x`"
24+
25+
// I3C_ASSERT_RPT is available to change the reporting mechanism when an assert fails
26+
`define I3C_ASSERT_RPT(name) \
27+
`ifdef UVM \
28+
uvm_pkg::uvm_report_error("I3C ASSERT FAILED", name, uvm_pkg::UVM_NONE, \
29+
`__FILE__, `__LINE__); \
30+
`else \
31+
$fatal(1, "[I3C_ASSERT FAILED] [%m] %s (%s:%0d)",name, `__FILE__, `__LINE__); \
32+
`endif
33+
34+
// Assert a concurrent property directly.
35+
`define I3C_ASSERT(assert_name, prop, clk = `I3C_ASSERT_DEFAULT_CLK, rst = `I3C_ASSERT_DEFAULT_RST) \
36+
`ifdef CLP_ASSERT_ON \
37+
assert_name: assert property (@(posedge clk) disable iff (rst !== 0) (prop)) \
38+
else begin \
39+
`I3C_ASSERT_RPT(`STRINGIFY(assert_name)) \
40+
end \
41+
`endif
42+
43+
// Assert a concurrent property NEVER happens
44+
`define I3C_ASSERT_NEVER(assert_name, prop, clk = `I3C_ASSERT_DEFAULT_CLK, rst = `I3C_ASSERT_DEFAULT_RST) \
45+
`ifdef CLP_ASSERT_ON \
46+
assert_name: assert property (@(posedge clk) disable iff (rst !== 0) not (prop)) \
47+
else begin \
48+
`I3C_ASSERT_RPT(`STRINGIFY(assert_name)) \
49+
end \
50+
`endif
51+
52+
// Assert that signal is not x
53+
`define I3C_ASSERT_KNOWN(assert_name, sig, clk = `I3C_ASSERT_DEFAULT_CLK, rst = `I3C_ASSERT_DEFAULT_RST) \
54+
`I3C_ASSERT(assert_name, !$isunknown(sig), clk, rst)
55+
56+
// Assert that a vector of signals is mutually exclusive
57+
`define I3C_ASSERT_MUTEX(assert_name, sig, clk = `I3C_ASSERT_DEFAULT_CLK, rst = `I3C_ASSERT_DEFAULT_RST) \
58+
`I3C_ASSERT(assert_name, $onehot0(sig), clk, rst)
59+
60+
`define I3C_ASSERT_INIT(__name, __prop)
61+
`endif

‎src/libs/mem/prim_generic_ram_1p.sv‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,8 @@
44
//
55
// Synchronous single-port SRAM model
66

7+
`include "i3c_sva.svh"
8+
79
module prim_generic_ram_1p import prim_ram_1p_pkg::*; #(
810
parameter int Width = 32, // bit
911
parameter int Depth = 128,
@@ -34,7 +36,7 @@ module prim_generic_ram_1p import prim_ram_1p_pkg::*; #(
3436
// `ifndef SYNTHESIS_MEMORY_BLACK_BOXING
3537

3638
// Width must be fully divisible by DataBitsPerMask
37-
`CALIPTRA_ASSERT_INIT(DataBitsPerMaskCheck_A, (Width % DataBitsPerMask) == 0)
39+
`I3C_ASSERT_INIT(DataBitsPerMaskCheck_A, (Width % DataBitsPerMask) == 0)
3840

3941
logic unused_cfg;
4042
assign unused_cfg = ^cfg_i;
@@ -50,7 +52,7 @@ module prim_generic_ram_1p import prim_ram_1p_pkg::*; #(
5052
assign wmask[k] = &wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
5153

5254
// Ensure that all mask bits within a group have the same value for a write
53-
`CALIPTRA_ASSERT(MaskCheck_A, req_i && write_i |->
55+
`I3C_ASSERT(MaskCheck_A, req_i && write_i |->
5456
wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
5557
clk_i, '0)
5658
end

‎src/libs/mem/prim_ram_1p_adv.sv‎

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,8 @@
1313
// Note that the write mask needs to be per Byte if parity is enabled. If ECC is enabled, the write
1414
// mask cannot be used and has to be tied to {Width{1'b1}}.
1515

16+
`include "i3c_sva.svh"
17+
1618
module prim_ram_1p_adv import prim_ram_1p_pkg::*; #(
1719
parameter int Depth = 512,
1820
parameter int Width = 32,
@@ -48,8 +50,7 @@ module prim_ram_1p_adv import prim_ram_1p_pkg::*; #(
4850
input ram_1p_cfg_t cfg_i
4951
);
5052

51-
52-
`CALIPTRA_ASSERT_INIT(CannotHaveEccAndParity_A, !(EnableParity && EnableECC))
53+
`I3C_ASSERT_INIT(CannotHaveEccAndParity_A, !(EnableParity && EnableECC))
5354

5455
// Calculate ECC width
5556
localparam int ParWidth = (EnableParity) ? Width/8 :
@@ -123,11 +124,11 @@ module prim_ram_1p_adv import prim_ram_1p_pkg::*; #(
123124
logic unused_wmask;
124125
assign unused_wmask = ^wmask_i;
125126

126-
// check supported widths
127-
`CALIPTRA_ASSERT_INIT(SecDecWidth_A, Width inside {16, 32})
127+
//I3Csupported widths
128+
`I3C_ASSERT_INIT(SecDecWidth_A, Width inside {16, 32})
128129

129-
// the wmask is constantly set to 1 in this case
130-
`CALIPTRA_ASSERT(OnlyWordWritePossibleWithEccPortA_A, req_i |->
130+
//I3Cask is constantly set to 1 in this case
131+
`I3C_ASSERT(OnlyWordWritePossibleWithEccPortA_A, req_i |->
131132
wmask_i == {Width{1'b1}})
132133

133134
assign wmask_d = {TotalWidth{1'b1}};
@@ -185,8 +186,8 @@ module prim_ram_1p_adv import prim_ram_1p_pkg::*; #(
185186

186187
end else if (EnableParity) begin : gen_byte_parity
187188

188-
`CALIPTRA_ASSERT_INIT(WidthNeedsToBeByteAligned_A, Width % 8 == 0)
189-
`CALIPTRA_ASSERT_INIT(ParityNeedsByteWriteMask_A, DataBitsPerMask == 8)
189+
`I3C_ASSERT_INIT(WidthNeedsToBeByteAligned_A, Width % 8 == 0)
190+
`I3C_ASSERT_INIT(ParityNeedsByteWriteMask_A, DataBitsPerMask == 8)
190191

191192
always_comb begin : p_parity
192193
rerror_d = '0;

‎tools/reg_gen/rdl_post_process.py‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@ def postprocess_sv(fname):
2828

2929
found_hard_reset = None
3030
declared_includes = False
31-
extra_includes = ["caliptra_sva.svh"]
31+
extra_includes = ["i3c_sva.svh"]
3232

3333
# Line by line manipulation
3434
# Look for unpacked arrays (could be struct arrays or signal arrays)
@@ -74,7 +74,7 @@ def postprocess_sv(fname):
7474
mod_cnt += 1
7575
elif is_endmodule is not None:
7676
mod_lines += "\n"
77-
mod_lines += "`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, !" + reset_name + ")\n"
77+
mod_lines += "`I3C_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, !" + reset_name + ")\n"
7878
mod_lines += "\n"
7979
mod_lines += line
8080
# Include caliptra asserts header

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