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robertszczepanskikgugala
robertszczepanski
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kgugala
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Update testplan
Signed-off-by: Wiktoria Kuna <[email protected]> Signed-off-by: Robert Szczepanski <[email protected]>
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-6
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8 files changed

+194
-6
lines changed

‎verification/cocotb/block/axi_adapter_id_filter/test_bus_stress.py‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -243,7 +243,7 @@ async def test_write_burst_collision_with_read_id_filter_on_priv(dut):
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@cocotb.test()
246-
async def test_write_burst_collision_with_read_id_filter_non_priv(dut):
246+
async def test_write_burst_collision_with_read_id_filter_on_non_priv(dut):
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await write_burst_collision_with_read(dut, False, Access.Priv, Access.Unpriv)
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‎verification/cocotb/block/axi_adapter_id_filter/test_seq_csr_access.py‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -122,7 +122,7 @@ async def test_write_to_controller_device_addr_filter_on_priv(dut):
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@cocotb.test()
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async def test_write_to_controller_device_addr_on_non_priv(dut):
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async def test_write_to_controller_device_addr_filter_on_non_priv(dut):
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priv_ids = draw_axi_priv_ids()
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tid = get_axi_ids_seq(priv_ids, 1, Access.Unpriv)[0]
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await write_to_controller_device_addr(dut, False, priv_ids, tid)
@@ -159,7 +159,7 @@ async def test_write_should_not_affect_ro_csr_filter_on_priv(dut):
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@cocotb.test()
162-
async def test_write_should_not_affect_ro_csr_on_non_priv(dut):
162+
async def test_write_should_not_affect_ro_csr_filter_on_non_priv(dut):
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priv_ids = draw_axi_priv_ids()
164164
tid = get_axi_ids_seq(priv_ids, 1, Access.Unpriv)[0]
165165
await write_should_not_affect_ro_csr(dut, False, priv_ids, tid)

‎verification/cocotb/top/lib_i3c_top/test_bypass.py‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -804,7 +804,12 @@ def csr_access_test_data(tb, rd_acc=Access.Priv, wr_acc=Access.Priv):
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return test_data
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806806

807-
@cocotb.test(skip=os.getenv("FrontendBusInterface") != "AXI")
807+
@cocotb.test(
808+
skip=(
809+
"FrontendBusInterface" not in cocotb.plusargs
810+
or cocotb.plusargs["FrontendBusInterface"] != "AXI"
811+
)
812+
)
808813
async def test_axi_filtering(dut):
809814
"""
810815
Verifies AXI ID filtering in Secure Firmware Recovery registers access.

‎verification/testplan/block/axi_filtering.hjson‎

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@@ -0,0 +1,82 @@
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{
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name: axi_filtering
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testpoints:
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[
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{
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name: axi_filtering_disabled
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desc:
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'''
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Verifies CSR access is granted when the AXI filtering feature is disabled.
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Verifies transaction response and contents.
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'''
13+
tests: ["read_hci_version_csr_id_filter_off",
14+
"read_pio_section_offset_filter_off",
15+
"write_to_controller_device_addr_filter_off",
16+
"write_should_not_affect_ro_csr_filter_off",
17+
"sequence_csr_read_filter_off",
18+
"sequence_csr_write_filter_off",
19+
"collision_with_write_id_filter_off",
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"collision_with_read_id_filter_off",
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"write_read_burst_id_filter_off",
22+
"write_burst_collision_with_read_id_filter_off",
23+
"read_burst_collision_with_write_id_filter_off"]
24+
tags: ["axi_filtering"]
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}
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{
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name: axi_filtering_priv
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desc:
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'''
30+
Verifies CSR access is granted when the AXI filtering is enabled
31+
and the transaction has a privileged ID.
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Verifies transaction response and contents.
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'''
34+
tests: ["read_hci_version_csr_id_filter_on_priv",
35+
"read_pio_section_offset_filter_on_priv",
36+
"write_to_controller_device_addr_filter_on_priv",
37+
"write_should_not_affect_ro_csr_filter_on_priv",
38+
"sequence_csr_read_filter_on_priv",
39+
"sequence_csr_write_filter_on_priv",
40+
"collision_with_write_id_filter_on_priv",
41+
"collision_with_read_id_filter_on_priv",
42+
"write_read_burst_id_filter_on_priv",
43+
"write_burst_collision_with_read_id_filter_on_priv",
44+
"read_burst_collision_with_write_id_filter_on_priv"]
45+
tags: ["axi_filtering"]
46+
}
47+
{
48+
name: axi_filtering_non_priv
49+
desc:
50+
'''
51+
Verifies CSR access is denied when the AXI filtering feature is enabled
52+
and the transaction ID doesn't match any of the privileged IDs.
53+
'''
54+
tests: ["read_hci_version_csr_id_filter_on_non_priv",
55+
"read_pio_section_offset_filter_on_non_priv",
56+
"write_to_controller_device_addr_filter_on_non_priv",
57+
"write_should_not_affect_ro_csr_filter_on_non_priv",
58+
"sequence_csr_read_filter_on_non_priv",
59+
"sequence_csr_write_filter_on_non_priv",
60+
"collision_with_write_id_filter_on_non_priv",
61+
"collision_with_read_id_filter_on_non_priv",
62+
"write_read_burst_id_filter_on_non_priv",
63+
"write_burst_collision_with_read_id_filter_on_non_priv",
64+
"read_burst_collision_with_write_id_filter_on_non_priv"]
65+
tags: ["axi_filtering"]
66+
}
67+
{
68+
name: axi_filtering_mixed_priv
69+
desc:
70+
'''
71+
Issues an ID-randomized colliding read and write transactions sequence.
72+
Verifies AXI CSR access response for each separate transaction.
73+
Ensures that access errors are raised only for unprivileged transactions.
74+
'''
75+
tests: ["collision_with_write_id_filter_on_mixed",
76+
"collision_with_read_id_filter_on_mixed",
77+
"collision_with_write_mixed_priv",
78+
"collision_with_read_mixed_priv"]
79+
tags: ["axi_filtering"]
80+
}
81+
]
82+
}

‎verification/testplan/block/csr_sw_access.hjson‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -43,4 +43,4 @@
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tags: ["adapter"]
4444
}
4545
]
46-
}
46+
}

‎verification/testplan/source-maps.yml‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,8 @@ testplans:
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- verification/cocotb/block/{name}/test_converter.py
1818
- Target:
1919
- verification/cocotb/top/lib_i3c_top/test_i3c_target.py
20+
- Recovery bypass:
21+
- verification/cocotb/top/lib_i3c_top/test_bypass.py
2022
- .*:
2123
- verification/cocotb/block/ctrl_{name}/test_{name}.py
2224
- verification/cocotb/block/{name}/test_{name}.py

‎verification/testplan/top/target_recovery_bypass.hjson‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,99 @@
1+
// SPDX-License-Identifier: Apache-2.0
2+
{
3+
name: Recovery bypass
4+
testpoints: [
5+
{
6+
name: simple_write_read
7+
desc: '''
8+
Verify basic bypass functionality
9+
- Enable I3C Core bypass in the Recovery Handler via CSR
10+
- Write to the TTI TX Data Queue and read from the Indirect FIFO Queue
11+
- Compare the data and verify it hasn't changed'''
12+
tests: ["indirect_fifo_write"]
13+
tags: ["top"]
14+
}
15+
{
16+
name: check_csr_access
17+
desc: '''
18+
Verify accessibility of CSRs as specified in the OCP Secure Firmware Recovery
19+
specification with additional bypass features
20+
- Write to all RW and read from all RO Secure Firmware Recovery Registers
21+
- Write to bypass registers with W1C property
22+
- Ensure the reserved fields of tested registers were not written
23+
- Ensure RW registers can be written and read back
24+
- Ensure RO registers cannot be written
25+
- Perform checks with bypass disabled and enabled'''
26+
tests: ["ocp_csr_access_bypass_enabled", "ocp_csr_access_bypass_disabled"]
27+
tags: ["top"]
28+
}
29+
{
30+
name: recovery_status_wires
31+
desc: '''
32+
Verify recovery status wires as specified in the Caliptra SS Hardware Specification
33+
- Write to the TTI TX Queue and read from the Indirect FIFO Queue.
34+
- Ensuring correct state of the `payload_available` wire
35+
- Write to the Recovery Control CSR to activate an image
36+
- Ensure correct state of the `image_activated` wire'''
37+
tests: ["payload_available", "image_activated"]
38+
tags: ["top"]
39+
}
40+
{
41+
name: indirect_fifo_overflow
42+
desc: '''
43+
Verify that access is rejected when the Indirect FIFO Queue overflows'''
44+
tests: ["indirect_fifo_overflow"]
45+
tags: ["top"]
46+
}
47+
{
48+
name: indirect_fifo_underflow
49+
desc: '''
50+
Verify that access is rejected when the Indirect FIFO Queue underflows'''
51+
tests: ["indirect_fifo_underflow"]
52+
tags: ["top"]
53+
}
54+
{
55+
name: i3c_bus_traffic_during_loopback
56+
desc: '''
57+
Verify that Recovery Handler with bypass enabled is not in any way interfered by any
58+
I3C bus traffic'''
59+
tests: ["i3c_bus_traffic_during_loopback"]
60+
tags: ["top"]
61+
}
62+
{
63+
name: check_axi_filtering
64+
desc: '''
65+
Verify that AXI access to Secure Firmware Recovery registers is filtered
66+
- AXI IDs from privileged ID list should always grant access to all registers
67+
- Once ID filtering is disabled, register access should be granted regardless of the
68+
transaction ID
69+
- With ID filtering enabled, all transactions with ID outside of the privileged ID list
70+
should be rejected with SLVERR response and register access request should not be
71+
propagated to the CPUIF'''
72+
tests: ["axi_filtering"]
73+
tags: ["top"]
74+
}
75+
{
76+
name: recovery_flow
77+
desc: '''
78+
Verify that Recovery Handler with bypass enabled can perform full Recovery Sequence
79+
as specified in the Caliptra Root of Trust specification'''
80+
tests: ["recovery_flow"]
81+
tags: ["top"]
82+
}
83+
{
84+
name: cptra_mcu_recovery
85+
desc: '''
86+
Verify that Caliptra Subsystem can perform full Recovery Sequence with I3C Core with
87+
bypass feature enabled. This test will run software on both Caliptra core and Caliptra
88+
MCU to interact with the I3C Core and Caliptra RoT.
89+
- MCU should initialize I3C Core with bypass enabled
90+
- Caliptra ROM should enable Recovery Mode
91+
- MCU should load image to Indirect FIFO Queue which will be read by Caliptra ROM
92+
- MCU should activate an image
93+
- Caliptra ROM should write an image to MCU SRAM
94+
- The image should be identical with the one read form simulated QSPI'''
95+
tests: ["cptra_mcu_recovery"]
96+
tags: ["top"]
97+
}
98+
]
99+
}

‎verification/testplan/top/target_reset.hjson‎

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@@ -15,4 +15,4 @@
1515
tags: ["top"]
1616
}
1717
]
18-
}
18+
}

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