Skip to content

Commit 329aa6c

Browse files
robertszczepanskikgugala
robertszczepanski
authored and
kgugala
committed
Add logic to restrict Indirect FIFO Queue access during bypass
Internal-tag: [#74211]
1 parent 37da564 commit 329aa6c

File tree

9 files changed

+294
-83
lines changed

9 files changed

+294
-83
lines changed

‎src/recovery/recovery_handler.sv‎

Lines changed: 23 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -388,6 +388,7 @@ module recovery_handler
388388
.source_flush_i(tti_tx_data_queue_flush_conv_source)
389389
);
390390

391+
logic allow_indirect_write, allow_indirect_read;
391392
// Data queues
392393
queues #(
393394

@@ -481,7 +482,7 @@ module recovery_handler
481482
.tx_rvalid_o(tti_tx_data_queue_rvalid),
482483
.tx_rready_i(tti_tx_data_queue_rready),
483484
.tx_rdata_o(tti_tx_data_queue_rdata),
484-
.tx_req_i(tti_tx_data_queue_req),
485+
.tx_req_i(tti_tx_data_queue_req & allow_indirect_write),
485486
.tx_ack_o(tti_tx_data_queue_ack),
486487
.tx_data_i(tti_tx_data_queue_data),
487488
.tx_start_thld_i(tti_tx_data_queue_start_thld),
@@ -492,9 +493,6 @@ module recovery_handler
492493
.tx_reg_rst_data_o(tti_tx_data_queue_reg_rst_next)
493494
);
494495

495-
// Recovery data available signal.
496-
// assign payload_available_o = recovery_enable & !tti_rx_data_queue_empty;
497-
498496
// IBI
499497
write_queue #(
500498

@@ -984,7 +982,7 @@ module recovery_handler
984982
.wdata_i (indirect_rx_wdata),
985983

986984
// Read port
987-
.req_i (indirect_rx_rreq),
985+
.req_i (indirect_rx_rreq & allow_indirect_read),
988986
.ack_o (indirect_rx_rack),
989987
.data_o(indirect_rx_rdata),
990988

@@ -1006,6 +1004,26 @@ module recovery_handler
10061004
.depth_o ()
10071005
);
10081006

1007+
always_ff @(posedge clk_i or negedge rst_ni) begin : indirect_fifo_access_permissions
1008+
if (~rst_ni) begin
1009+
allow_indirect_write <= '0;
1010+
allow_indirect_read <= '0;
1011+
end else begin
1012+
if (bypass_i3c_core_i) begin
1013+
if (indirect_rx_empty) begin
1014+
allow_indirect_write <= 1'b1;
1015+
allow_indirect_read <= 1'b0;
1016+
end else if (indirect_rx_full | payload_available_o) begin
1017+
allow_indirect_write <= 1'b0;
1018+
allow_indirect_read <= 1'b1;
1019+
end
1020+
end else begin
1021+
allow_indirect_write <= 1'b1;
1022+
allow_indirect_read <= 1'b1;
1023+
end
1024+
end
1025+
end
1026+
10091027
// ....................................................
10101028

10111029
logic exec_tti_rx_data_ready;

‎verification/cocotb/block/axi_adapter/test_bus_stress.py‎

Lines changed: 25 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -3,18 +3,12 @@
33
import logging
44
import random
55

6-
from bus2csr import (
7-
dword2int,
8-
get_frontend_bus_if,
9-
int2bytes,
10-
int2dword,
11-
)
6+
from bus2csr import dword2int, get_frontend_bus_if, int2bytes, int2dword
7+
from cocotb_helpers import reset_n
8+
from cocotbext.axi.constants import AxiBurstType
129

1310
import cocotb
1411
from cocotb.triggers import ClockCycles, Combine, RisingEdge, Timer, with_timeout
15-
from cocotb_helpers import reset_n
16-
17-
from cocotbext.axi.constants import AxiBurstType
1812

1913

2014
async def timeout_task(timeout):
@@ -167,10 +161,14 @@ async def test_write_read_burst(dut):
167161
raddr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
168162

169163
# Run write burst to fill the FIFO
170-
await with_timeout(tb.axi_m.write_dwords(waddr, test_data, burst=AxiBurstType.FIXED), 1, "us")
164+
await with_timeout(
165+
tb.axi_m.write_dwords(waddr, test_data, burst=AxiBurstType.FIXED), 1, "us"
166+
)
171167

172168
# Run read burst to empty the FIFO
173-
received_data = await with_timeout(tb.axi_m.read_dwords(raddr, count=data_len, burst=AxiBurstType.FIXED), 1, "us")
169+
received_data = await with_timeout(
170+
tb.axi_m.read_dwords(raddr, count=data_len, burst=AxiBurstType.FIXED), 1, "us"
171+
)
174172

175173
assert received_data == test_data, "Received data does not match sent data!"
176174

@@ -188,10 +186,16 @@ async def test_write_burst_collision_with_read(dut):
188186
single_write_cycles = 3
189187

190188
async def writer():
191-
await with_timeout(tb.axi_m.write_dwords(waddr, test_data, burst=AxiBurstType.FIXED), 1, "us")
189+
await with_timeout(
190+
tb.axi_m.write_dwords(waddr, test_data, burst=AxiBurstType.FIXED), 1, "us"
191+
)
192192

193193
async def reader(return_data):
194-
return_data.extend(await with_timeout(tb.axi_m.read_dwords(raddr, count=data_len, burst=AxiBurstType.FIXED), 1, "us"))
194+
return_data.extend(
195+
await with_timeout(
196+
tb.axi_m.read_dwords(raddr, count=data_len, burst=AxiBurstType.FIXED), 1, "us"
197+
)
198+
)
195199

196200
received_data = []
197201
half_write_timer = ClockCycles(tb.clk, data_len * single_write_cycles // 2)
@@ -221,10 +225,16 @@ async def test_read_burst_collision_with_write(dut):
221225
single_write_cycles = 3
222226

223227
async def writer():
224-
await with_timeout(tb.axi_m.write_dwords(waddr, test_data, burst=AxiBurstType.FIXED), 1, "us")
228+
await with_timeout(
229+
tb.axi_m.write_dwords(waddr, test_data, burst=AxiBurstType.FIXED), 1, "us"
230+
)
225231

226232
async def reader(return_data):
227-
return_data.extend(await with_timeout(tb.axi_m.read_dwords(raddr, count=data_len, burst=AxiBurstType.FIXED), 1, "us"))
233+
return_data.extend(
234+
await with_timeout(
235+
tb.axi_m.read_dwords(raddr, count=data_len, burst=AxiBurstType.FIXED), 1, "us"
236+
)
237+
)
228238

229239
received_data1 = []
230240
received_data2 = []

‎verification/cocotb/block/hci_queues_ahb/hci_queues_wrapper.sv‎

Lines changed: 26 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -441,6 +441,7 @@ module hci_queues_wrapper
441441
logic csr_tti_tx_data_queue_reg_rst;
442442
logic csr_tti_tx_data_queue_reg_rst_we;
443443
logic csr_tti_tx_data_queue_reg_rst_data;
444+
logic csr_tti_tx_data_queue_full;
444445

445446
// TTI In-band Interrupt (IBI) queue
446447
logic csr_tti_ibi_queue_req;
@@ -451,6 +452,8 @@ module hci_queues_wrapper
451452
logic csr_tti_ibi_queue_reg_rst_we;
452453
logic csr_tti_ibi_queue_reg_rst_data;
453454

455+
logic unused_irq;
456+
454457
tti xtti (
455458
.clk_i (hclk),
456459
.rst_ni(hreset_n),
@@ -499,6 +502,7 @@ module hci_queues_wrapper
499502
.tx_data_queue_reg_rst_o (csr_tti_tx_data_queue_reg_rst),
500503
.tx_data_queue_reg_rst_we_i (csr_tti_tx_data_queue_reg_rst_we),
501504
.tx_data_queue_reg_rst_data_i(csr_tti_tx_data_queue_reg_rst_data),
505+
.tx_data_queue_full_i (csr_tti_tx_data_queue_full),
502506

503507
// TTI In-band Interrupt (IBI) queue
504508
.ibi_queue_req_o (csr_tti_ibi_queue_req),
@@ -507,7 +511,27 @@ module hci_queues_wrapper
507511
.ibi_queue_ready_thld_o (csr_tti_ibi_queue_ready_thld),
508512
.ibi_queue_reg_rst_o (csr_tti_ibi_queue_reg_rst),
509513
.ibi_queue_reg_rst_we_i (csr_tti_ibi_queue_reg_rst_we),
510-
.ibi_queue_reg_rst_data_i(csr_tti_ibi_queue_reg_rst_data)
514+
.ibi_queue_reg_rst_data_i(csr_tti_ibi_queue_reg_rst_data),
515+
516+
.bypass_i3c_core_i,
517+
518+
.ibi_status_i('0),
519+
.ibi_status_we_i('0),
520+
.recovery_mode_enabled_i('0),
521+
.tx_pr_end_i('0),
522+
523+
.enec_ibi_i('0),
524+
.enec_crr_i('0),
525+
.enec_hj_i('0),
526+
527+
.disec_ibi_i('0),
528+
.disec_crr_i('0),
529+
.disec_hj_i('0),
530+
531+
.err_i('0),
532+
533+
// Interrupt
534+
.irq_o(unused_irq)
511535
);
512536

513537
// Recovery handler
@@ -575,6 +599,7 @@ module hci_queues_wrapper
575599
.csr_tti_tx_data_queue_reg_rst_i (csr_tti_tx_data_queue_reg_rst),
576600
.csr_tti_tx_data_queue_reg_rst_we_o (csr_tti_tx_data_queue_reg_rst_we),
577601
.csr_tti_tx_data_queue_reg_rst_data_o(csr_tti_tx_data_queue_reg_rst_data),
602+
.csr_tti_tx_data_queue_full_o (csr_tti_tx_data_queue_full),
578603

579604
// TTI In-band Interrupt (IBI) queue
580605
.csr_tti_ibi_queue_req_i (csr_tti_ibi_queue_req),

‎verification/cocotb/block/hci_queues_axi/hci_queues_wrapper.sv‎

Lines changed: 26 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -513,6 +513,7 @@ module hci_queues_wrapper
513513
logic csr_tti_tx_data_queue_reg_rst;
514514
logic csr_tti_tx_data_queue_reg_rst_we;
515515
logic csr_tti_tx_data_queue_reg_rst_data;
516+
logic csr_tti_tx_data_queue_full;
516517

517518
// TTI In-band Interrupt (IBI) queue
518519
logic csr_tti_ibi_queue_req;
@@ -523,6 +524,8 @@ module hci_queues_wrapper
523524
logic csr_tti_ibi_queue_reg_rst_we;
524525
logic csr_tti_ibi_queue_reg_rst_data;
525526

527+
logic unused_irq;
528+
526529
tti xtti (
527530
.clk_i (aclk),
528531
.rst_ni(areset_n),
@@ -571,6 +574,7 @@ module hci_queues_wrapper
571574
.tx_data_queue_reg_rst_o (csr_tti_tx_data_queue_reg_rst),
572575
.tx_data_queue_reg_rst_we_i (csr_tti_tx_data_queue_reg_rst_we),
573576
.tx_data_queue_reg_rst_data_i(csr_tti_tx_data_queue_reg_rst_data),
577+
.tx_data_queue_full_i (csr_tti_tx_data_queue_full),
574578

575579
// TTI In-band Interrupt (IBI) queue
576580
.ibi_queue_req_o (csr_tti_ibi_queue_req),
@@ -579,7 +583,27 @@ module hci_queues_wrapper
579583
.ibi_queue_ready_thld_o (csr_tti_ibi_queue_ready_thld),
580584
.ibi_queue_reg_rst_o (csr_tti_ibi_queue_reg_rst),
581585
.ibi_queue_reg_rst_we_i (csr_tti_ibi_queue_reg_rst_we),
582-
.ibi_queue_reg_rst_data_i(csr_tti_ibi_queue_reg_rst_data)
586+
.ibi_queue_reg_rst_data_i(csr_tti_ibi_queue_reg_rst_data),
587+
588+
.bypass_i3c_core_i,
589+
590+
.ibi_status_i('0),
591+
.ibi_status_we_i('0),
592+
.recovery_mode_enabled_i('0),
593+
.tx_pr_end_i('0),
594+
595+
.enec_ibi_i('0),
596+
.enec_crr_i('0),
597+
.enec_hj_i('0),
598+
599+
.disec_ibi_i('0),
600+
.disec_crr_i('0),
601+
.disec_hj_i('0),
602+
603+
.err_i('0),
604+
605+
// Interrupt
606+
.irq_o(unused_irq)
583607
);
584608

585609
// Recovery handler
@@ -647,6 +671,7 @@ module hci_queues_wrapper
647671
.csr_tti_tx_data_queue_reg_rst_i (csr_tti_tx_data_queue_reg_rst),
648672
.csr_tti_tx_data_queue_reg_rst_we_o (csr_tti_tx_data_queue_reg_rst_we),
649673
.csr_tti_tx_data_queue_reg_rst_data_o(csr_tti_tx_data_queue_reg_rst_data),
674+
.csr_tti_tx_data_queue_full_o (csr_tti_tx_data_queue_full),
650675

651676
// TTI In-band Interrupt (IBI) queue
652677
.csr_tti_ibi_queue_req_i (csr_tti_ibi_queue_req),

‎verification/cocotb/block/lib_hci_queues/tti_queues.py‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@ async def setup(self):
2929
self.dut.tti_ibi_rready_i.value = 0
3030
self.dut.tti_rx_flush_i.value = 0
3131
self.dut.tti_tx_flush_i.value = 0
32+
self.dut.bypass_i3c_core_i.value = 0
3233

3334
await super()._setup(get_frontend_bus_if())
3435

‎verification/cocotb/top/lib_i3c_top/interface.py‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,6 @@
55
from reg_map import reg_map
66

77
import cocotb
8-
from cocotb.clock import Clock
98
from cocotb.handle import SimHandleBase
109
from cocotb.triggers import ClockCycles
1110

0 commit comments

Comments
 (0)