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Add TE0 and TE1 timeout tests
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
1 parent 6a29975 commit 37f7052

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5 files changed

+102
-12
lines changed

5 files changed

+102
-12
lines changed

‎src/ctrl/bus_timers.sv‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ module bus_timers
2626
input logic clk_i,
2727
input logic rst_ni,
2828
input logic enable_i,
29-
input logic restart_counter_i,
29+
input logic reset_counter_ni,
3030
input logic [19:0] t_bus_free_i, // CSR: Time to free
3131
input logic [19:0] t_bus_idle_i, // CSR: Time to idle
3232
input logic [19:0] t_bus_available_i, // CSR: Time to available
@@ -40,7 +40,7 @@ module bus_timers
4040
logic enable;
4141
always_ff @(posedge clk_i or negedge rst_ni) begin : proc_enable
4242
if (!rst_ni) begin
43-
enable <= '0;
43+
enable <= '1;
4444
end else begin
4545
enable <= enable_i & ~bus_idle_o;
4646
end
@@ -50,7 +50,7 @@ module bus_timers
5050
if (!rst_ni) begin
5151
bus_state_counter <= '0;
5252
end else begin
53-
if (restart_counter_i) begin
53+
if (!reset_counter_ni) begin
5454
bus_state_counter <= '0;
5555
end else begin
5656
if (enable) begin

‎src/ctrl/ccc.sv‎

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -426,12 +426,13 @@ module ccc
426426
RxDataTbit,
427427
TxData,
428428
TxDataTbit,
429-
WaitForBusCond,
429+
WaitForBusCond, // 0x0F
430430
NextCCC,
431431
DoneCCC,
432432
HandleENTDAA,
433433
HandleTargetENTDAA,
434434
HandleVirtualTargetENTDAA,
435+
HandleDoneENTDAA,
435436
CCCError
436437
} state_e;
437438

@@ -683,23 +684,25 @@ module ccc
683684
end else if (~virtual_target_dyn_address_valid_i) begin
684685
state_d = HandleVirtualTargetENTDAA;
685686
end else begin
686-
state_d = Idle;
687+
state_d = HandleDoneENTDAA;
687688
end
688689
end
689690
HandleTargetENTDAA: begin
690691
if (entdaa_done) begin
691692
if (~virtual_target_dyn_address_valid_i) begin
692693
state_d = HandleVirtualTargetENTDAA;
693694
end else begin
694-
state_d = Idle;
695+
state_d = HandleDoneENTDAA;
695696
end
696697
end
697698
end
698699
HandleVirtualTargetENTDAA: begin
699700
if (entdaa_done) begin
700-
state_d = Idle;
701+
state_d = HandleDoneENTDAA;
701702
end
702703
end
704+
HandleDoneENTDAA: begin
705+
end
703706
RxDefByte: begin
704707
if (bus_rx_done_i) state_d = RxDefByteTbit;
705708
end

‎src/ctrl/controller_standby_i3c.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -660,7 +660,7 @@ module controller_standby_i3c
660660
.clk_i,
661661
.rst_ni,
662662
.enable_i (i3c_standby_en),
663-
.restart_counter_i(ctrl_bus_i.stop_det),
663+
.reset_counter_ni (ctrl_bus_i.scl.value & ctrl_bus_i.sda.value),
664664
.t_bus_free_i (t_bus_free_i),
665665
.t_bus_idle_i (t_bus_idle_i),
666666
.t_bus_available_i(t_bus_available_i),

‎verification/cocotb/block/ctrl_bus_timers/test_bus_timers.py‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ async def setup(dut):
1818
dut.t_bus_free_i.value = 5
1919
dut.t_bus_available_i.value = 10
2020
dut.t_bus_idle_i.value = 50
21-
dut.restart_counter_i.value = 0
21+
dut.reset_counter_ni.value = 1
2222
await ClockCycles(dut.clk_i, 10)
2323

2424

@@ -41,7 +41,7 @@ async def test_bus_timers(dut: SimHandleBase):
4141
dut.enable_i.value = 1
4242

4343
for _ in range(3):
44-
await cycle(dut.clk_i, dut.restart_counter_i)
44+
await cycle(dut.clk_i, dut.reset_counter_ni)
4545
await ClockCycles(dut.clk_i, 1)
4646
assert dut.bus_free_o.value == 0
4747
assert dut.bus_available_o.value == 0

‎verification/cocotb/top/lib_i3c_top/test_err_conds.py‎

Lines changed: 89 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
from math import ceil
1313

1414
import cocotb
15-
from cocotb.triggers import ClockCycles
15+
from cocotb.triggers import ClockCycles, Timer
1616
from cocotb.regression import TestFactory
1717

1818
TGT_ADR = 0x5A
@@ -95,6 +95,51 @@ async def test_TE0_HDR_exit(dut):
9595
== 0xa2
9696
) # WaitHDRExitOrIdle
9797
await i3c_controller.send_hdr_exit()
98+
i3c_controller.give_bus_control()
99+
assert (
100+
int(dut.xi3c_wrapper.i3c.xcontroller.xcontroller_standby.xcontroller_standby_i3c.xi3c_target_fsm.state_d.value)
101+
== 0
102+
) # Idle
103+
104+
105+
@cocotb.test()
106+
async def test_TE0_idle_exit(dut):
107+
108+
(STATIC_ADDR, VIRT_STATIC_ADDR, DYNAMIC_ADDR, VIRT_DYNAMIC_ADDR) = random.sample(VALID_I3C_ADDRESSES, 4)
109+
ADDRs = [random.choice([STATIC_ADDR, DYNAMIC_ADDR]), random.choice([VIRT_STATIC_ADDR, VIRT_DYNAMIC_ADDR])]
110+
111+
i3c_controller, i3c_target, tb = await test_setup(dut, STATIC_ADDR, VIRT_STATIC_ADDR,
112+
dynamic_addr=DYNAMIC_ADDR, virtual_dynamic_addr=VIRT_DYNAMIC_ADDR)
113+
await ClockCycles(tb.clk, 50)
114+
115+
idle_time_in_cycles = ceil(60000 / (1000 / FCLK))
116+
await tb.write_csr_field(
117+
tb.reg_map.I3C_EC.SOCMGMTIF.T_IDLE_REG.base_addr,
118+
tb.reg_map.I3C_EC.SOCMGMTIF.T_IDLE_REG.T_IDLE,
119+
idle_time_in_cycles
120+
)
121+
122+
incorrect_addrs = [
123+
(0x3E, True), (0x5E, True), (0x6E, True), (0x76, True), (0x7A, True),
124+
(0x7C, True), (0x7F, True), (0x7E, False)
125+
]
126+
127+
for _ in range(2):
128+
addr, write = random.choice(incorrect_addrs)
129+
assert (
130+
int(dut.xi3c_wrapper.i3c.xcontroller.xcontroller_standby.xcontroller_standby_i3c.xi3c_target_fsm.state_d.value)
131+
== 0
132+
) # Idle
133+
await i3c_controller.take_bus_control()
134+
await i3c_controller.send_start()
135+
ack = await i3c_controller.write_addr_header(addr, read=not write)
136+
await i3c_controller.send_stop()
137+
i3c_controller.give_bus_control()
138+
assert (
139+
int(dut.xi3c_wrapper.i3c.xcontroller.xcontroller_standby.xcontroller_standby_i3c.xi3c_target_fsm.state_d.value)
140+
== 0xa2
141+
) # WaitHDRExitOrIdle
142+
await Timer(60, "us")
98143
assert (
99144
int(dut.xi3c_wrapper.i3c.xcontroller.xcontroller_standby.xcontroller_standby_i3c.xi3c_target_fsm.state_d.value)
100145
== 0
@@ -133,6 +178,46 @@ async def test_TE1_HDR_exit(dut):
133178
== 0xa2
134179
) # WaitHDRExitOrIdle
135180
await i3c_controller.send_hdr_exit()
181+
i3c_controller.give_bus_control()
182+
assert (
183+
int(dut.xi3c_wrapper.i3c.xcontroller.xcontroller_standby.xcontroller_standby_i3c.xi3c_target_fsm.state_d.value)
184+
== 0
185+
) # Idle
186+
187+
188+
@cocotb.test()
189+
async def test_TE1_idle_exit(dut):
190+
191+
(STATIC_ADDR, VIRT_STATIC_ADDR, DYNAMIC_ADDR, VIRT_DYNAMIC_ADDR) = random.sample(VALID_I3C_ADDRESSES, 4)
192+
ADDRs = [random.choice([STATIC_ADDR, DYNAMIC_ADDR]), random.choice([VIRT_STATIC_ADDR, VIRT_DYNAMIC_ADDR])]
193+
194+
i3c_controller, i3c_target, tb = await test_setup(dut, STATIC_ADDR, VIRT_STATIC_ADDR,
195+
dynamic_addr=DYNAMIC_ADDR, virtual_dynamic_addr=VIRT_DYNAMIC_ADDR)
196+
await ClockCycles(tb.clk, 50)
197+
198+
idle_time_in_cycles = ceil(60000 / (1000 / FCLK))
199+
await tb.write_csr_field(
200+
tb.reg_map.I3C_EC.SOCMGMTIF.T_IDLE_REG.base_addr,
201+
tb.reg_map.I3C_EC.SOCMGMTIF.T_IDLE_REG.T_IDLE,
202+
idle_time_in_cycles
203+
)
204+
205+
for _ in range(2):
206+
assert (
207+
int(dut.xi3c_wrapper.i3c.xcontroller.xcontroller_standby.xcontroller_standby_i3c.xi3c_target_fsm.state_d.value)
208+
== 0
209+
) # Idle
210+
await i3c_controller.take_bus_control()
211+
await i3c_controller.send_start()
212+
ack = await i3c_controller.write_addr_header(0x7E, read=False)
213+
await i3c_controller.send_byte_tbit(random.randint(0, 0xFF), True)
214+
await i3c_controller.send_stop()
215+
i3c_controller.give_bus_control()
216+
assert (
217+
int(dut.xi3c_wrapper.i3c.xcontroller.xcontroller_standby.xcontroller_standby_i3c.xi3c_target_fsm.state_d.value)
218+
== 0xa2
219+
) # WaitHDRExitOrIdle
220+
await Timer(60, "us")
136221
assert (
137222
int(dut.xi3c_wrapper.i3c.xcontroller.xcontroller_standby.xcontroller_standby_i3c.xi3c_target_fsm.state_d.value)
138223
== 0
@@ -150,7 +235,7 @@ async def test_TE5_read_on_write(dut):
150235

151236
COMMANDs = [0x87, 0x88, 0x89, 0x8A, 0x80, 0x81, 0x98]
152237

153-
for _ in range(random.randint(10, 15)):
238+
for _ in range(2):
154239
assert (
155240
int(dut.xi3c_wrapper.i3c.xcontroller.xcontroller_standby.xcontroller_standby_i3c.xi3c_target_fsm.state_d.value)
156241
== 0
@@ -164,6 +249,7 @@ async def test_TE5_read_on_write(dut):
164249
ack = await i3c_controller.write_addr_header(DYNAMIC_ADDR, read=True)
165250
assert ack == False
166251
await i3c_controller.send_stop()
252+
i3c_controller.give_bus_control()
167253
assert (
168254
int(dut.xi3c_wrapper.i3c.xcontroller.xcontroller_standby.xcontroller_standby_i3c.xi3c_target_fsm.state_d.value)
169255
== 0
@@ -199,6 +285,7 @@ async def test_TE5_write_on_read(dut):
199285
ack = await i3c_controller.write_addr_header(DYNAMIC_ADDR, read=False)
200286
assert ack == False
201287
await i3c_controller.send_stop()
288+
i3c_controller.give_bus_control()
202289
assert (
203290
int(dut.xi3c_wrapper.i3c.xcontroller.xcontroller_standby.xcontroller_standby_i3c.xi3c_target_fsm.state_d.value)
204291
== 0

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