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testplan: Update 'test' and 'tags' syntax
Signed-off-by: Wiktoria Kuna <[email protected]>
1 parent e5e4b53 commit 416404a

24 files changed

+239
-953
lines changed

‎verification/testplan/block/bus_monitor.hjson‎

Lines changed: 2 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -11,14 +11,8 @@
1111
and a simulated target. Counts start, repeated start and stop events
1212
reported by bus_monitor. Verifies that the counts match what's expected.
1313
'''
14-
tests:
15-
[
16-
bus_monitor
17-
]
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tags:
19-
[
20-
bus_monitor
21-
]
14+
tests: ["bus_monitor"]
15+
tags: ["bus_monitor"]
2216
}
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]
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}

‎verification/testplan/block/bus_rx_flow.hjson‎

Lines changed: 4 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -10,14 +10,8 @@
1010
requests, verifies that the module returns correct data sampled
1111
from the SDA line.
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'''
13-
tests:
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[
15-
multiple_bit_reads
16-
]
17-
tags:
18-
[
19-
bus_rx_flow
20-
]
13+
tests: ["multiple_bit_reads"]
14+
tags: ["bus_rx_flow"]
2115
}
2216
{
2317
name: multiple_byte_reads
@@ -27,14 +21,8 @@
2721
requests, verifies that the module returns correct data sampled
2822
from the SDA line.
2923
'''
30-
tests:
31-
[
32-
multiple_byte_reads
33-
]
34-
tags:
35-
[
36-
bus_rx_flow
37-
]
24+
tests: ["multiple_byte_reads"]
25+
tags: ["bus_rx_flow"]
3826
}
3927
]
4028
}

‎verification/testplan/block/bus_timers.hjson‎

Lines changed: 2 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -11,14 +11,8 @@
1111
the signals corresponding to bus states get asserted after the
1212
required time period.
1313
'''
14-
tests:
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[
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bus_timers
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]
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tags:
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[
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bus_timers
21-
]
14+
tests: ["bus_timers"]
15+
tags: ["bus_timers"]
2216
}
2317
]
2418
}

‎verification/testplan/block/bus_tx.hjson‎

Lines changed: 10 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -9,14 +9,8 @@
99
Requests the bus_tx module to drive SDA right after SCL falling
1010
edge. Checks if the requested bit value is driven correctly
1111
'''
12-
tests:
13-
[
14-
bit_tx_negedge
15-
]
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tags:
17-
[
18-
bus_tx
19-
]
12+
tests: ["bit_tx_negedge"]
13+
tags: ["bus_tx"]
2014
}
2115
{
2216
name: bit_tx_pre_posedge
@@ -25,14 +19,8 @@
2519
Requests the bus_tx module to drive SDA just before SCL rising
2620
edge. Checks if the requested bit value is driven correctly
2721
'''
28-
tests:
29-
[
30-
bit_tx_pre_posedge
31-
]
32-
tags:
33-
[
34-
bus_tx
35-
]
22+
tests: ["bit_tx_pre_posedge"]
23+
tags: ["bus_tx"]
3624
}
3725
{
3826
name: bit_tx_high_level
@@ -41,14 +29,8 @@
4129
Requests the bus_tx module to drive SDA just before SCL falling
4230
edge. Checks if the requested bit value is driven correctly
4331
'''
44-
tests:
45-
[
46-
bit_tx_high_level
47-
]
48-
tags:
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[
50-
bus_tx
51-
]
32+
tests: ["bit_tx_high_level"]
33+
tags: ["bus_tx"]
5234
}
5335
{
5436
name: bit_tx_low_level
@@ -57,14 +39,8 @@
5739
Requests the bus_tx module to drive SDA when SCL in in stable
5840
low state. Checks if the requested bit value is driven correctly
5941
'''
60-
tests:
61-
[
62-
bit_tx_low_level
63-
]
64-
tags:
65-
[
66-
bus_tx
67-
]
42+
tests: ["bit_tx_low_level"]
43+
tags: ["bus_tx"]
6844
}
6945
{
7046
name: byte_tx
@@ -74,14 +50,8 @@
7450
a data byte plus T bit to the I3C bus. For each bit sent checks
7551
if SDA is driven correctly and bus timings are met.
7652
'''
77-
tests:
78-
[
79-
byte_tx
80-
]
81-
tags:
82-
[
83-
bus_tx
84-
]
53+
tests: ["byte_tx"]
54+
tags: ["bus_tx"]
8555
}
8656
]
8757
}

‎verification/testplan/block/bus_tx_flow.hjson‎

Lines changed: 11 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -9,14 +9,8 @@
99
Requests the bus_tx_flow module to drive SDA right after SCL falling
1010
edge. Checks if the requested bit value is driven correctly
1111
'''
12-
tests:
13-
[
14-
bit_tx_negedge
15-
]
16-
tags:
17-
[
18-
bus_tx_flow
19-
]
12+
tests: ["bit_tx_negedge"]
13+
tags: ["bus_tx_flow"]
2014
}
2115
{
2216
name: bit_tx_pre_posedge
@@ -25,14 +19,8 @@
2519
Requests the bus_tx_flow module to drive SDA just before SCL rising
2620
edge. Checks if the requested bit value is driven correctly
2721
'''
28-
tests:
29-
[
30-
bit_tx_pre_posedge
31-
]
32-
tags:
33-
[
34-
bus_tx_flow
35-
]
22+
tests: ["bit_tx_pre_posedge"]
23+
tags: ["bus_tx_flow"]
3624
}
3725
{
3826
name: bit_tx_high_level
@@ -41,14 +29,8 @@
4129
Requests the bus_tx_flow module to drive SDA just before SCL falling
4230
edge. Checks if the requested bit value is driven correctly
4331
'''
44-
tests:
45-
[
46-
bit_tx_high_level
47-
]
48-
tags:
49-
[
50-
bus_tx_flow
51-
]
32+
tests: ["bit_tx_high_level"]
33+
tags: ["bus_tx_flow"]
5234
}
5335
{
5436
name: bit_tx_low_level
@@ -57,32 +39,20 @@
5739
Requests the bus_tx_flow module to drive SDA when SCL in in stable
5840
low state. Checks if the requested bit value is driven correctly
5941
'''
60-
tests:
61-
[
62-
bit_tx_low_level
63-
]
64-
tags:
65-
[
66-
bus_tx_flow
67-
]
42+
tests: ["bit_tx_low_level"]
43+
tags: ["bus_tx_flow"]
6844
}
6945
{
7046
name: byte_tx
7147
desc:
7248
'''
73-
Requests the bus_tx_flow module to transmitt a data byte along with
49+
Requests the bus_tx_flow module to transmit a data byte along with
7450
T-bit. While the transmission is in progress samples SDA on rising
7551
edges of SCL. Once the transmission finishes compares sampled data
7652
with what was requested to be sent.
7753
'''
78-
tests:
79-
[
80-
byte_tx
81-
]
82-
tags:
83-
[
84-
bus_tx_flow
85-
]
54+
tests: ["byte_tx"]
55+
tags: ["bus_tx_flow"]
8656
}
8757
]
8858
}

‎verification/testplan/block/ccc.hjson‎

Lines changed: 2 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -11,14 +11,8 @@
1111
to mimick actual I3C transaction. Checks if data bytes received
1212
correspond to correct GETSTATUS CCC response.
1313
'''
14-
tests:
15-
[
16-
ccc
17-
]
18-
tags:
19-
[
20-
ccc
21-
]
14+
tests: ["ccc"]
15+
tags: ["ccc"]
2216
}
2317
]
2418
}

‎verification/testplan/block/csr_sw_access.hjson‎

Lines changed: 12 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -5,38 +5,20 @@
55
{
66
name: read_hci_version_csr
77
desc: Reads the HCI version CSR and verifies its content
8-
tests:
9-
[
10-
read_hci_version_csr
11-
]
12-
tags:
13-
[
14-
adapter
15-
]
8+
tests: ["read_hci_version_csr"]
9+
tags: ["adapter"]
1610
}
1711
{
1812
name: read_pio_section_offset
1913
desc: Reads the PIO_SECTION_OFFSET CSR and verifies its content
20-
tests:
21-
[
22-
read_pio_section_offset
23-
]
24-
tags:
25-
[
26-
adapter
27-
]
14+
tests: ["read_pio_section_offset"]
15+
tags: ["adapter"]
2816
}
2917
{
3018
name: write_to_controller_device_addr
3119
desc: "Writes to the CONTROLLER_DEVICE_ADDR CSR and verifies if the write was successful "
32-
tests:
33-
[
34-
write_to_controller_device_addr
35-
]
36-
tags:
37-
[
38-
adapter
39-
]
20+
tests: ["write_to_controller_device_addr"]
21+
tags: ["adapter"]
4022
}
4123
{
4224
name: write_should_not_affect_ro_csr
@@ -45,38 +27,20 @@
4527
Writes to the HC_CAPABILITIES CSR which is read-only for software
4628
Verifies that the write did not succeed.
4729
'''
48-
tests:
49-
[
50-
write_should_not_affect_ro_csr
51-
]
52-
tags:
53-
[
54-
adapter
55-
]
30+
tests: ["write_should_not_affect_ro_csr"]
31+
tags: ["adapter"]
5632
}
5733
{
5834
name: sequence_csr_read
5935
desc: Performs a sequence of CSR reads. Verifies that each one succeeds
60-
tests:
61-
[
62-
sequence_csr_read
63-
]
64-
tags:
65-
[
66-
adapter
67-
]
36+
tests: ["sequence_csr_read"]
37+
tags: ["adapter"]
6838
}
6939
{
7040
name: sequence_csr_write
7141
desc: Performs a sequence of CSR writes. Verifies that each one succeeds
72-
tests:
73-
[
74-
sequence_csr_write
75-
]
76-
tags:
77-
[
78-
adapter
79-
]
42+
tests: ["sequence_csr_write"]
43+
tags: ["adapter"]
8044
}
8145
]
8246
}

‎verification/testplan/block/descriptor_rx.hjson‎

Lines changed: 2 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -10,14 +10,8 @@
1010
descriptors. The test sends N bytes to the module and verifies
1111
that it emits a valid descriptor with data length set to N.
1212
'''
13-
tests:
14-
[
15-
descriptor_rx
16-
]
17-
tags:
18-
[
19-
descriptor_rx
20-
]
13+
tests: ["descriptor_rx"]
14+
tags: ["descriptor_rx"]
2115
}
2216
]
2317
}

‎verification/testplan/block/descriptor_tx.hjson‎

Lines changed: 2 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -12,14 +12,8 @@
1212
amount of data. Verifies that the module accepted the descriptor
1313
and allowed the right amount of data bytes to pass through it.
1414
'''
15-
tests:
16-
[
17-
descriptor_tx
18-
]
19-
tags:
20-
[
21-
descriptor_tx
22-
]
15+
tests: ["descriptor_tx"]
16+
tags: ["descriptor_tx"]
2317
}
2418
]
2519
}

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