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Import axi_sub code from caliptra-rtl
This commit imports 'axi_sub' code from caliptra-rtl repository. Caliptra-ref: a4582f5856136286d2389b1cfa8de2910a82fe5e Signed-off-by: Maciej Dudek <[email protected]>
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9 files changed

+1232
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lines changed

‎src/i3c.f‎

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@@ -17,12 +17,8 @@
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${CALIPTRA_ROOT}/src/libs/rtl/ahb_slv_sif.sv
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${CALIPTRA_ROOT}/src/axi/rtl/axi_pkg.sv
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${CALIPTRA_ROOT}/src/axi/rtl/axi_if.sv
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${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_arb.sv
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${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_rd.sv
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${CALIPTRA_ROOT}/src/axi/rtl/axi_sub.sv
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${CALIPTRA_ROOT}/src/axi/rtl/axi_addr.v
2421
${CALIPTRA_ROOT}/src/libs/rtl/skidbuffer.v
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${CALIPTRA_ROOT}/src/axi/rtl/axi_sub_wr.sv
2622
${I3C_ROOT_DIR}/src/libs/mem/prim_ram_1p_pkg.sv
2723
${I3C_ROOT_DIR}/src/libs/mem/prim_generic_ram_1p.sv
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${I3C_ROOT_DIR}/src/libs/mem/prim_ram_1p_adv.sv
@@ -36,6 +32,10 @@
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${I3C_ROOT_DIR}/src/phy/i3c_io.sv
3733
${I3C_ROOT_DIR}/src/csr/I3CCSR.sv
3834
${I3C_ROOT_DIR}/src/interrupt.sv
35+
${I3C_ROOT_DIR}/src/libs/axi_sub/axi_sub_arb.sv
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${I3C_ROOT_DIR}/src/libs/axi_sub/axi_sub_rd.sv
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${I3C_ROOT_DIR}/src/libs/axi_sub/axi_sub.sv
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${I3C_ROOT_DIR}/src/libs/axi_sub/axi_sub_wr.sv
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${I3C_ROOT_DIR}/src/hci/queues/read_queue.sv
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${I3C_ROOT_DIR}/src/hci/queues/write_queue.sv
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${I3C_ROOT_DIR}/src/hci/ahb_if.sv

‎src/libs/axi_sub/axi_sub.sv‎

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// SPDX-License-Identifier: Apache-2.0
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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//
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// -------------------------------------------------------------
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// AXI Subordinate
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// -------------------------------------------------------------
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// Description:
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// Subordinate to convert AXI protocol transactions into internal component accesses
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// Includes an arbiter to squash duplex AXI transactions into simplex component operations
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// May optionally include an Exclusive Access monitor (AxLOCK signal)
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//
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// Limitations:
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// - When multiple ID tracking is enabled, write responses are returned in the
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// same order they are received, regardless of ID.
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//
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// -------------------------------------------------------------
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module axi_sub import axi_pkg::*; #(
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parameter AW = 32, // Address Width
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parameter DW = 32, // Data Width
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BC = DW/8, // Byte Count
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BW = $clog2(BC), // Byte count Width
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parameter UW = 32, // User Width
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parameter IW = 1, // ID Width
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ID_NUM = 1 << IW, // Don't override
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parameter EX_EN = 0, // Enable exclusive access tracking w/ AxLOCK
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parameter C_LAT = 0 // Component latency in clock cycles from (dv&&!hld) -> rdata
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// Must be const per component
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// For registers, typically 0
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// For SRAM, 1 or more
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) (
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input clk,
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input rst_n,
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// AXI INF
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axi_if.w_sub s_axi_w_if,
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axi_if.r_sub s_axi_r_if,
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//COMPONENT INF
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output logic dv,
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output logic [AW-1:0] addr, // Byte address
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output logic write,
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output logic [UW-1:0] user,
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output logic [IW-1:0] id,
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output logic [DW-1:0] wdata, // Requires: Component dwidth == AXI dwidth
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output logic [BC-1:0] wstrb, // Requires: Component dwidth == AXI dwidth
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output logic [2:0] size,
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input logic [DW-1:0] rdata, // Requires: Component dwidth == AXI dwidth
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output logic last, // Asserted with final 'dv' of a burst
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input logic hld,
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input logic rd_err,
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input logic wr_err
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);
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// Exclusive Access Signals
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`ifdef CALIPTRA_AXI_SUB_EX_EN
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logic [ID_NUM-1:0] ex_clr;
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logic [ID_NUM-1:0] ex_active;
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struct packed {
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logic [AW-1:0] addr;
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logic [AW-1:0] addr_mask;
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} [ID_NUM-1:0] ex_ctx;
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`endif
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//Read Subordinate INF
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logic r_dv;
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logic [AW-1:0] r_addr; // Byte address
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logic [UW-1:0] r_user;
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logic [IW-1:0] r_id;
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logic [2:0] r_size;
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logic r_last; // Asserted with final 'dv' of a burst
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logic r_hld;
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logic r_err;
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logic [DW-1:0] r_rdata; // Requires: Component dwidth == AXI dwidth
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//Write Subordinate INF
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logic w_dv;
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logic [AW-1:0] w_addr; // Byte address
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logic [UW-1:0] w_user;
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logic [IW-1:0] w_id;
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logic [DW-1:0] w_wdata; // Requires: Component dwidth == AXI dwidth
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logic [BC-1:0] w_wstrb; // Requires: Component dwidth == AXI dwidth
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logic [2:0] w_size;
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logic w_last; // Asserted with final 'dv' of a burst
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logic w_hld;
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logic w_err;
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axi_sub_wr #(
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.AW (AW ),
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.DW (DW ),
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.UW (UW ),
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.IW (IW )
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) i_axi_sub_wr (
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.clk (clk ),
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.rst_n(rst_n),
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// AXI INF
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.s_axi_if(s_axi_w_if),
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// Exclusive Access Signals
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`ifdef CALIPTRA_AXI_SUB_EX_EN
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.ex_clr (ex_clr ),
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.ex_active(ex_active),
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.ex_ctx (ex_ctx ),
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`endif
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//COMPONENT INF
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.dv (w_dv ),
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.addr (w_addr ),
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.user (w_user ),
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.id (w_id ),
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.wdata(w_wdata),
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.wstrb(w_wstrb),
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.wsize(w_size ),
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.last (w_last ),
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.hld (w_hld ),
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.err (w_err )
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);
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axi_sub_rd #(
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.AW(AW),
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.DW(DW),
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.UW(UW),
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.IW(IW),
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.C_LAT(C_LAT)
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) i_axi_sub_rd (
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.clk (clk ),
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.rst_n(rst_n),
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// AXI INF
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.s_axi_if(s_axi_r_if),
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// Exclusive Access Signals
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`ifdef CALIPTRA_AXI_SUB_EX_EN
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.ex_clr (ex_clr ),
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.ex_active(ex_active),
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.ex_ctx (ex_ctx ),
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`endif
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//COMPONENT INF
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.dv (r_dv ),
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.addr (r_addr ),
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.user (r_user ),
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.id (r_id ),
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.size (r_size ),
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.last (r_last ),
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.hld (r_hld ),
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.err (r_err ),
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.rdata(r_rdata)
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);
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axi_sub_arb #(
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.AW(AW),
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.DW(DW),
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.UW(UW),
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.IW(IW),
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.C_LAT(C_LAT)
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) i_axi_sub_arb (
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.clk (clk ),
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.rst_n (rst_n ),
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//Read Subordinate INF
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.r_dv (r_dv ),
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.r_addr (r_addr ),
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.r_user (r_user ),
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.r_id (r_id ),
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.r_last (r_last ),
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.r_size (r_size ),
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.r_hld (r_hld ),
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.r_err (r_err ),
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.r_rdata(r_rdata),
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//Write Subordinate INF
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.w_dv (w_dv ),
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.w_addr (w_addr ),
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.w_user (w_user ),
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.w_id (w_id ),
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.w_wdata(w_wdata),
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.w_wstrb(w_wstrb),
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.w_size (w_size ),
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.w_last (w_last ),
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.w_hld (w_hld ),
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.w_err (w_err ),
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//COMPONENT INF
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.dv (dv ),
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.addr (addr ),
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.write (write ),
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.user (user ),
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.id (id ),
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.wdata (wdata ),
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.wstrb (wstrb ),
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.size (size ),
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.last (last ),
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.hld (hld ),
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.rd_err (rd_err ),
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.wr_err (wr_err ),
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.rdata (rdata )
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);
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endmodule

‎src/libs/axi_sub/axi_sub_arb.sv‎

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// SPDX-License-Identifier: Apache-2.0
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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// -------------------------------------------------------------
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// AXI Subordinate Arbiter
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// -------------------------------------------------------------
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// Description:
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// Arbitrate between Reads and Writes coming from AXI subordinate modules.
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// Always give precedence to Writes.
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//
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// -------------------------------------------------------------
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module axi_sub_arb import axi_pkg::*; #(
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parameter AW = 32, // Address Width
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parameter DW = 32, // Data Width
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BC = DW/8, // Byte Count
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BW = $clog2(BC), // Byte count Width
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parameter UW = 32, // User Width
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parameter IW = 1, // ID Width
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ID_NUM = 1 << IW, // Don't override
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34+
parameter C_LAT = 0 // Component latency in clock cycles from (dv&&!hld) -> rdata
35+
// Must be const per component
36+
// For registers, typically 0
37+
// For SRAM, 1 or more
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) (
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input clk,
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input rst_n,
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//Read Subordinate INF
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input logic r_dv,
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input logic [AW-1:0] r_addr, // Byte address
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input logic [UW-1:0] r_user,
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input logic [IW-1:0] r_id,
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input logic [2:0] r_size,
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input logic r_last, // Asserted with final 'dv' of a burst
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output logic r_hld,
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output logic r_err,
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output logic [DW-1:0] r_rdata, // Requires: Component dwidth == AXI dwidth
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//Write Subordinate INF
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input logic w_dv,
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input logic [AW-1:0] w_addr, // Byte address
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input logic [UW-1:0] w_user,
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input logic [IW-1:0] w_id,
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input logic [DW-1:0] w_wdata, // Requires: Component dwidth == AXI dwidth
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input logic [BC-1:0] w_wstrb, // Requires: Component dwidth == AXI dwidth
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input logic [2:0] w_size,
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input logic w_last, // Asserted with final 'dv' of a burst
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output logic w_hld,
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output logic w_err,
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//COMPONENT INF
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output logic dv,
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output logic [AW-1:0] addr, // Byte address
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output logic write,
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output logic [UW-1:0] user,
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output logic [IW-1:0] id,
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output logic [DW-1:0] wdata, // Requires: Component dwidth == AXI dwidth
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output logic [BC-1:0] wstrb, // Requires: Component dwidth == AXI dwidth
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output logic [2:0] size,
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output logic last, // Asserted with final 'dv' of a burst
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input logic hld,
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input logic rd_err, // Asserts with rdata for reads (when C_LAT > 0)
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input logic wr_err, // Asserts with dv for writes
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input logic [DW-1:0] rdata // Requires: Component dwidth == AXI dwidth
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);
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`include "caliptra_prim_assert.sv"
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logic r_pri; // Priority to reads
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logic r_win;
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// Switch priority to current arb winner so that priority persists
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// in case
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// a) it was granted during a hold
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// b) it was granted at start of multi-beat burst
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// Otherwise, always give priority to other channel at end of a burst
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// to arbitrate fairly
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always_ff@(posedge clk or negedge rst_n) begin
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if (!rst_n)
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r_pri <= 1'b0;
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// Toggle priority at end of burst
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else if (w_dv && !w_hld && w_last)
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r_pri <= 1'b1;
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else if (r_dv && !r_hld && r_last)
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r_pri <= 1'b0;
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// Keep priority when xfer is in progress
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else if (w_dv && !r_win)
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r_pri <= 1'b0;
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else if (r_dv && r_win)
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r_pri <= 1'b1;
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end
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always_comb begin
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// case ({r_pri,r_dv,w_dv}) inside
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// 3'b000: r_win = 0;
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// 3'b001: r_win = 0;
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// 3'b010: r_win = 1;
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// 3'b011: r_win = 0;
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// 3'b100: r_win = 1;
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// 3'b101: r_win = 0;
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// 3'b110: r_win = 1;
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// 3'b111: r_win = 1;
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// endcase
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if (r_pri) r_win = r_dv || !w_dv;
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else r_win = r_dv && !w_dv;
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end
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always_comb begin
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dv = r_dv || w_dv;
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addr = r_win ? r_addr : w_addr;
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write = r_win ? 0 : 1;
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user = r_win ? r_user : w_user;
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id = r_win ? r_id : w_id ;
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last = r_win ? r_last : w_last;
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size = r_win ? r_size : w_size;
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r_hld = hld || !r_win;
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w_hld = hld || r_win;
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r_err = rd_err;
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w_err = wr_err;
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wdata = w_wdata;
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wstrb = w_wstrb;
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r_rdata = rdata;
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end
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`CALIPTRA_ASSERT_NEVER(AXI_SUB_ARB_CONFLICT, r_dv && !r_hld && w_dv && !w_hld, clk, !rst_n)
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endmodule

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