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robertszczepanskitmichalak
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Test cleanup
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verification/cocotb/block/axi_adapter/test_bus_stress.py

Lines changed: 20 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -4,18 +4,14 @@
44
import random
55

66
from bus2csr import (
7-
FrontBusTestInterface,
8-
compare_values,
97
dword2int,
108
get_frontend_bus_if,
119
int2bytes,
1210
int2dword,
1311
)
14-
from utils import mask_bits, rand_bits, rand_bits32
1512

1613
import cocotb
17-
from cocotb.handle import SimHandleBase
18-
from cocotb.triggers import ClockCycles, Combine, Event, RisingEdge, Timer, with_timeout
14+
from cocotb.triggers import ClockCycles, Combine, RisingEdge, Timer, with_timeout
1915
from cocotb_helpers import reset_n
2016

2117
from cocotbext.axi.constants import AxiBurstType
@@ -29,7 +25,7 @@ async def timeout_task(timeout):
2925
async def initialize(dut, timeout=50):
3026
"""
3127
Common test initialization routine which sets up environment and starts a timeout coroutine
32-
to observe whether the test did not fall in infinite loop.
28+
to observe whether the test did not fall into infinite loop.
3329
"""
3430

3531
cocotb.log.setLevel(logging.DEBUG)
@@ -69,6 +65,7 @@ async def initialize(dut, timeout=50):
6965
await ClockCycles(tb.clk, 20)
7066
await reset_n(tb.clk, tb.rst_n, cycles=5)
7167

68+
# Generate test data
7269
data_len = random.randint(10, 64)
7370
test_data = [random.randint(0, 2**32 - 1) for _ in range(data_len)]
7471

@@ -87,7 +84,7 @@ async def writer():
8784
# Write sequence should just write data
8885
for d in test_data:
8986
await tb.write_csr(fifo_addr, int2bytes(d))
90-
# Wait for read to finish to avoid multiple writes per read
87+
# Wait for read to finish in order to avoid multiple writes per read
9188
await tb.axi_m.wait_read()
9289

9390
async def reader(return_data):
@@ -120,11 +117,14 @@ async def test_collision_with_read(dut):
120117

121118
fifo_addr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
122119

120+
read_offset = 2
121+
123122
async def writer():
124123
# Write sequence should write data on each read data
125124
for i, d in enumerate(test_data):
126-
# Awaiting read request causes writing simultaneously with read data channel activity
127-
if i > 2:
125+
# Load first two dwords independently
126+
if i > read_offset:
127+
# Awaiting read request causes writing simultaneously with read data channel activity
128128
await RisingEdge(dut.s_cpuif_req)
129129
assert not dut.s_cpuif_req_is_wr.value
130130
# Wait additional cycle to line up write with FIFO read delay
@@ -133,7 +133,6 @@ async def writer():
133133

134134
async def reader(return_data):
135135
# Wait until there is data in FIFO
136-
read_offset = 2
137136
while int(dut.fifo_depth_o.value) < read_offset:
138137
await RisingEdge(tb.clk)
139138

@@ -161,7 +160,10 @@ async def test_write_read_burst(dut):
161160

162161
fifo_addr = tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr
163162

163+
# Run write burst to fill the FIFO
164164
await with_timeout(tb.axi_m.write_dwords(fifo_addr, test_data, burst=AxiBurstType.FIXED), 1, "us")
165+
166+
# Run read burst to empty the FIFO
165167
received_data = await with_timeout(tb.axi_m.read_dwords(fifo_addr, count=data_len, burst=AxiBurstType.FIXED), 1, "us")
166168

167169
assert received_data == test_data, "Received data does not match sent data!"
@@ -187,9 +189,13 @@ async def reader(return_data):
187189
received_data = []
188190
half_write_timer = ClockCycles(tb.clk, data_len * single_write_cycles // 2)
189191

192+
# Request write burst
190193
w = cocotb.start_soon(writer())
191194
await half_write_timer
195+
196+
# Request read burst during write burst, should wait for write to finish
192197
r = cocotb.start_soon(reader(received_data))
198+
193199
await Combine(w, r)
194200

195201
assert received_data == test_data, "Received data does not match sent data!"
@@ -219,14 +225,18 @@ async def reader(return_data):
219225
# Request 1st write burst
220226
w1 = cocotb.start_soon(writer())
221227
await half_write_timer
228+
222229
# Request 1st read burst during 1st write burst, should wait for write to finish
223230
r1 = cocotb.start_soon(reader(received_data1))
224231
await half_write_timer
232+
225233
# Request 2nd write burst that will collision with 1st read burst, should wait for read to finish
226234
w2 = cocotb.start_soon(writer())
227235
await half_write_timer
236+
228237
# Request 2nd read burst during 2nd write burst, should wait for write to finish
229238
r2 = cocotb.start_soon(reader(received_data2))
239+
230240
await Combine(w1, r1, w2, r2)
231241

232242
assert received_data1 == test_data, "Received data from 1st burst does not match sent data!"

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