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SETMRL: keep IBI value
Release IBI mux on arbitration loss Signed-off-by: Maciej Dudek <[email protected]>
1 parent 2847e76 commit 5b328eb

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6 files changed

+53
-11
lines changed

6 files changed

+53
-11
lines changed

‎src/ctrl/ccc.sv‎

Lines changed: 24 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -167,6 +167,10 @@ module ccc
167167
output logic set_mrl_o,
168168
output logic [15:0] mrl_o,
169169

170+
// Set Max Read Length
171+
output logic set_ibil_o,
172+
output logic [7:0] ibil_o,
173+
170174
// Enter Test Mode
171175
output logic ent_tm_o,
172176
output logic [7:0] tm_o,
@@ -230,6 +234,10 @@ module ccc
230234
// I3C_DIRECT_GETMRL
231235
input logic [15:0] get_mrl_i,
232236

237+
// Get Max IBI Length
238+
// I3C_DIRECT_GETMRL
239+
input logic [7:0] get_ibil_i,
240+
233241
// Get Provisioned ID
234242
// I3C_DIRECT_GETPID
235243
input logic [47:0] get_pid_i,
@@ -497,8 +505,9 @@ module ccc
497505

498506
logic unsupported_def_byte;
499507

500-
assign unsupported_def_byte = have_defining_byte & (
501-
(command_code == `I3C_DIRECT_RSTACT) & ~(defining_byte inside {8'h00, 8'h01, 8'h02, 8'h81, 8'h82}));
508+
assign unsupported_def_byte = have_defining_byte & valid_defining_byte & (
509+
(command_code == `I3C_DIRECT_RSTACT) & ~(defining_byte inside {8'h00, 8'h01, 8'h02, 8'h81, 8'h82})
510+
| (command_code == `I3C_DIRECT_GETCAPS));
502511

503512
logic supported_direct_command;
504513
assign supported_direct_command = supported_direct_command_code & ~unsupported_def_byte;
@@ -843,9 +852,7 @@ module ccc
843852
tx_data_id_init = 8'h03;
844853
if (tx_data_id == 8'h03) tx_data = get_mrl_i[15:8];
845854
else if (tx_data_id == 8'h02) tx_data = get_mrl_i[7:0];
846-
else if (tx_data_id == 8'h01)
847-
// Maximum IBI payload size is 256 Bytes
848-
tx_data = '1;
855+
else if (tx_data_id == 8'h01) tx_data = get_ibil_i;
849856
else tx_data = '0;
850857
end
851858
`I3C_DIRECT_GETPID: begin
@@ -934,6 +941,8 @@ module ccc
934941
if (~rst_ni) begin
935942
set_mrl_o <= 1'b0;
936943
mrl_o <= '0;
944+
set_ibil_o <= 1'b0;
945+
ibil_o <= '1;
937946
set_mwl_o <= 1'b0;
938947
mwl_o <= '0;
939948
enec_ibi <= '0;
@@ -953,7 +962,7 @@ module ccc
953962
case (command_code)
954963
// setmwl
955964
`I3C_DIRECT_SETMWL, `I3C_BCAST_SETMWL: begin
956-
if (state_q == RxDataTbit && bus_rx_done_i && ~is_byte_rsvd_addr) begin
965+
if (state_q == RxDataTbit && bus_rx_done_i && (~is_byte_rsvd_addr || command_code == `I3C_BCAST_SETMWL)) begin
957966
if (rx_data_count == 8'd0) begin
958967
mwl_o[15:8] <= rx_data;
959968
set_mwl_o <= 1'b0;
@@ -969,17 +978,25 @@ module ccc
969978
end
970979
// setmrl
971980
`I3C_DIRECT_SETMRL, `I3C_BCAST_SETMRL: begin
972-
if (state_q == RxDataTbit && bus_rx_done_i && ~is_byte_rsvd_addr) begin
981+
if (state_q == RxDataTbit && bus_rx_done_i && (~is_byte_rsvd_addr || command_code == `I3C_BCAST_SETMRL)) begin
973982
if (rx_data_count == 8'd0) begin
974983
mrl_o[15:8] <= rx_data;
984+
set_ibil_o <= 1'b0;
975985
set_mrl_o <= 1'b0;
976986
end else if (rx_data_count == 8'd1) begin
977987
mrl_o[7:0] <= rx_data;
988+
set_ibil_o <= 1'b0;
978989
set_mrl_o <= 1'b1;
990+
end else if (rx_data_count == 8'd2) begin
991+
ibil_o[7:0] <= rx_data;
992+
set_ibil_o <= 1'b1;
993+
set_mrl_o <= 1'b0;
979994
end else begin
995+
set_ibil_o <= 1'b0;
980996
set_mrl_o <= 1'b0;
981997
end
982998
end else begin
999+
set_ibil_o <= 1'b0;
9831000
set_mrl_o <= 1'b0;
9841001
end
9851002
end

‎src/ctrl/configuration.sv‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@ module configuration (
3030

3131
output logic [15:0] get_mwl_o, // Get Max Write Length
3232
output logic [15:0] get_mrl_o, // Get Max Read Length
33+
output logic [ 7:0] get_ibil_o, // Get Max IBI Length
3334
output logic [15:0] get_status_fmt1_o, // Get Status Format 1
3435

3536
output logic [47:0] pid_o, // Target ID
@@ -63,8 +64,10 @@ module configuration (
6364

6465
input logic set_mwl_i,
6566
input logic set_mrl_i,
67+
input logic set_ibil_i,
6668
input logic [15:0] mwl_i,
67-
input logic [15:0] mrl_i
69+
input logic [15:0] mrl_i,
70+
input logic [ 7:0] ibil_i
6871
);
6972

7073
// Mode of operation
@@ -158,9 +161,11 @@ module configuration (
158161
if (~rst_ni) begin
159162
get_mwl_o <= 16'd256;
160163
get_mrl_o <= 16'd256;
164+
get_ibil_o <= 8'd255;
161165
end else begin
162166
if (set_mwl_i) get_mwl_o <= mwl_i;
163167
if (set_mrl_i) get_mrl_o <= mrl_i;
168+
if (set_ibil_i) get_ibil_o <= ibil_i;
164169
end
165170
end
166171

‎src/ctrl/controller.sv‎

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -264,6 +264,7 @@ module controller
264264
logic [19:0] t_bus_available;
265265
logic [15:0] get_mwl;
266266
logic [15:0] get_mrl;
267+
logic [7:0] get_ibil;
267268
logic [15:0] get_status_fmt1;
268269
logic [47:0] pid;
269270
logic [7:0] bcr;
@@ -283,8 +284,9 @@ module controller
283284
logic target_ibi_addr_valid;
284285
logic [6:0] target_hot_join_addr;
285286
logic [63:0] daa_unique_response;
286-
logic set_mwl, set_mrl;
287+
logic set_mwl, set_mrl, set_ibil;
287288
logic [15:0] mwl, mrl;
289+
logic [7:0] ibil;
288290

289291
logic ibi_enable;
290292
logic [2:0] ibi_retry_num;
@@ -353,6 +355,7 @@ module controller
353355
.t_bus_available_o (t_bus_available),
354356
.get_mwl_o (get_mwl),
355357
.get_mrl_o (get_mrl),
358+
.get_ibil_o (get_ibil),
356359
.get_status_fmt1_o (get_status_fmt1),
357360
.pid_o (pid),
358361
.bcr_o (bcr),
@@ -376,8 +379,10 @@ module controller
376379
.ibi_retry_num_o (ibi_retry_num),
377380
.set_mwl_i (set_mwl),
378381
.set_mrl_i (set_mrl),
382+
.set_ibil_i (set_ibil),
379383
.mwl_i (mwl),
380-
.mrl_i (mrl)
384+
.mrl_i (mrl),
385+
.ibil_i (ibil)
381386
);
382387

383388
assign recovery_mode = (hwif_rec_i.DEVICE_STATUS_0.DEV_STATUS.value == RecoveryMode);
@@ -534,6 +539,7 @@ module controller
534539
.t_bus_available_i(t_bus_available),
535540
.get_mwl_i(get_mwl),
536541
.get_mrl_i(get_mrl),
542+
.get_ibil_i(get_ibil),
537543
.get_status_fmt1_i(get_status_fmt1),
538544
.pid_i(pid),
539545
.bcr_i(bcr),
@@ -580,8 +586,10 @@ module controller
580586
.err_o,
581587
.set_mwl_o(set_mwl),
582588
.set_mrl_o(set_mrl),
589+
.set_ibil_o(set_ibil),
583590
.mwl_o(mwl),
584591
.mrl_o(mrl),
592+
.ibil_o(ibil),
585593
.peripheral_reset_o,
586594
.peripheral_reset_done_i,
587595
.escalated_reset_o,

‎src/ctrl/controller_standby.sv‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -119,6 +119,7 @@ module controller_standby
119119
input logic [19:0] t_bus_available_i,
120120
input logic [15:0] get_mwl_i,
121121
input logic [15:0] get_mrl_i,
122+
input logic [ 7:0] get_ibil_i,
122123
input logic [15:0] get_status_fmt1_i,
123124
input logic [47:0] pid_i,
124125
input logic [7:0] bcr_i,
@@ -166,8 +167,10 @@ module controller_standby
166167

167168
output logic set_mwl_o,
168169
output logic set_mrl_o,
170+
output logic set_ibil_o,
169171
output logic [15:0] mwl_o,
170172
output logic [15:0] mrl_o,
173+
output logic [07:0] ibil_o,
171174

172175
output logic [1:0] ibi_status_o,
173176
output logic ibi_status_we_o,
@@ -428,6 +431,7 @@ module controller_standby
428431
.t_bus_available_i(t_bus_available_i),
429432
.get_mwl_i(get_mwl_i),
430433
.get_mrl_i(get_mrl_i),
434+
.get_ibil_i(get_ibil_i),
431435
.get_status_fmt1_i(get_status_fmt1_i),
432436
.pid_i(pid_i),
433437
.bcr_i(bcr_i),
@@ -470,8 +474,10 @@ module controller_standby
470474
.disec_hj_o(disec_hj_o),
471475
.set_mwl_o(set_mwl_o),
472476
.set_mrl_o(set_mrl_o),
477+
.set_ibil_o(set_ibil_o),
473478
.mwl_o(mwl_o),
474479
.mrl_o(mrl_o),
480+
.ibil_o(ibil_o),
475481
.rstdaa_o(rstdaa_o),
476482
.ibi_status_o(ibi_status_o),
477483
.ibi_status_we_o(ibi_status_we_o),

‎src/ctrl/controller_standby_i3c.sv‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -72,6 +72,7 @@ module controller_standby_i3c
7272
input logic [19:0] t_bus_available_i,
7373
input logic [15:0] get_mwl_i,
7474
input logic [15:0] get_mrl_i,
75+
input logic [7:0] get_ibil_i,
7576
input logic [15:0] get_status_fmt1_i,
7677
input logic [47:0] pid_i,
7778
input logic [7:0] bcr_i,
@@ -119,8 +120,10 @@ module controller_standby_i3c
119120

120121
output logic set_mwl_o,
121122
output logic set_mrl_o,
123+
output logic set_ibil_o,
122124
output logic [15:0] mwl_o,
123125
output logic [15:0] mrl_o,
126+
output logic [7:0] ibil_o,
124127

125128
output logic [1:0] ibi_status_o,
126129
output logic ibi_status_we_o,
@@ -517,6 +520,8 @@ module controller_standby_i3c
517520
.mwl_o (mwl_o),
518521
.set_mrl_o (set_mrl_o),
519522
.mrl_o (mrl_o),
523+
.set_ibil_o (set_ibil_o),
524+
.ibil_o (ibil_o),
520525
.ent_tm_o (ent_tm),
521526
.tm_o (tm),
522527
.ent_hdr_0_o (ent_hdr_0),
@@ -539,6 +544,7 @@ module controller_standby_i3c
539544
.newda_o,
540545
.get_mwl_i (get_mwl_i),
541546
.get_mrl_i (get_mrl_i),
547+
.get_ibil_i (get_ibil_i),
542548
.get_pid_i (pid_i),
543549
.get_bcr_i (bcr_i),
544550
.get_dcr_i (dcr_i),

‎src/ctrl/ibi.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -273,7 +273,7 @@ module ibi (
273273
(ibi_retry_num_i != ibi_retry_cnt);
274274

275275

276-
assign done_o = (state_q == Done);
276+
assign done_o = (state_q == Done || (state_q == DriveAddr && arbitration_lost_i && ~bus_tx_done_i));
277277

278278
assign ibi_status_o = ibi_status;
279279
assign ibi_status_we_o = (state_q == Done) | ((state_q == WaitStopOrRstart) & bus_stop_i);

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