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robertszczepanskitmichalak
robertszczepanski
authored and
tmichalak
committed
Update AXI Subordinate
1 parent dc3afa3 commit 5b343ab

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7 files changed

+299
-175
lines changed

7 files changed

+299
-175
lines changed

‎src/libs/axi/axi_addr.v‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,9 @@
1919
// Creator: Dan Gisselquist, Ph.D.
2020
// Gisselquist Technology, LLC
2121
//
22+
// Caliptra Modifications:
23+
// Revert the default_nettype assignment at file end
24+
//
2225
////////////////////////////////////////////////////////////////////////////////
2326
// }}}
2427
// Copyright (C) 2019-2024, Gisselquist Technology, LLC
@@ -233,3 +236,4 @@ module axi_addr #(
233236
// Verilator lint_on UNUSED
234237
// }}}
235238
endmodule
239+
`default_nettype wire

‎src/libs/axi/axi_if.sv‎

Lines changed: 55 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616
// Signals for a standard AXI4 compliant interface
1717
//
1818

19-
interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, parameter integer IW = 3, parameter integer UW = 32) (input logic clk, input logic rst_n);
19+
interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, parameter integer IW = 8, parameter integer UW = 32) (input logic clk, input logic rst_n);
2020

2121
import axi_pkg::*;
2222

@@ -35,6 +35,7 @@ interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, paramet
3535
logic [DW-1:0] rdata;
3636
logic [$bits(axi_resp_e)-1:0] rresp;
3737
logic [IW-1:0] rid;
38+
logic [UW-1:0] ruser;
3839
logic rlast;
3940
logic rvalid;
4041
logic rready;
@@ -53,13 +54,15 @@ interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, paramet
5354
// AXI W
5455
logic [DW-1:0] wdata;
5556
logic [DW/8-1:0] wstrb;
57+
logic [UW-1:0] wuser;
5658
logic wvalid;
5759
logic wready;
5860
logic wlast;
5961

6062
// AXI B
6163
logic [$bits(axi_resp_e)-1:0] bresp;
6264
logic [IW-1:0] bid;
65+
logic [UW-1:0] buser;
6366
logic bvalid;
6467
logic bready;
6568

@@ -79,6 +82,7 @@ interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, paramet
7982
input rdata,
8083
input rresp,
8184
input rid,
85+
input ruser,
8286
input rlast,
8387
input rvalid,
8488
output rready
@@ -99,12 +103,14 @@ interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, paramet
99103
// W
100104
output wdata,
101105
output wstrb,
106+
output wuser,
102107
output wvalid,
103108
input wready,
104109
output wlast,
105110
// B
106111
input bresp,
107112
input bid,
113+
input buser,
108114
input bvalid,
109115
output bready
110116
);
@@ -125,6 +131,7 @@ interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, paramet
125131
output rdata,
126132
output rresp,
127133
output rid,
134+
output ruser,
128135
output rlast,
129136
output rvalid,
130137
input rready
@@ -145,16 +152,20 @@ interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, paramet
145152
// W
146153
input wdata,
147154
input wstrb,
155+
input wuser,
148156
input wvalid,
149157
output wready,
150158
input wlast,
151159
// B
152160
output bresp,
153161
output bid,
162+
output buser,
154163
output bvalid,
155164
input bready
156165
);
157166

167+
// synopsys translate_off
168+
158169
// Tasks
159170
`ifdef VERILATOR
160171
`define EQ__ =
@@ -186,6 +197,7 @@ interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, paramet
186197

187198
wdata `EQ__ '0;
188199
wstrb `EQ__ '0;
200+
wuser `EQ__ '0;
189201
wvalid `EQ__ '0;
190202
wlast `EQ__ '0;
191203

@@ -194,13 +206,15 @@ interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, paramet
194206

195207
// TODO: handle IDs?
196208
task get_read_beat(output logic [DW-1:0] data,
209+
output logic [UW-1:0] user,
197210
output axi_resp_e resp);
198211
`TIME_ALGN
199212
rready `EQ__ 1;
200213
do
201214
@(posedge clk);
202215
while (!rvalid);
203216
data `EQ__ rdata;
217+
user `EQ__ ruser;
204218
resp `EQ__ axi_resp_e'(rresp);
205219
`TIME_ALGN
206220
rready `EQ__ 0;
@@ -216,8 +230,10 @@ interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, paramet
216230
input logic [IW-1:0] id = IW'(0),
217231
input logic lock = 1'b0,
218232
output logic [DW-1:0] data [],
233+
output logic [UW-1:0] resp_user [],
219234
output axi_resp_e resp []);
220235
axi_resp_e beat_resp;
236+
logic [UW-1:0] beat_user;
221237
logic [DW-1:0] beat_data;
222238
while(!rst_n) @(posedge clk);
223239
do begin
@@ -244,9 +260,10 @@ interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, paramet
244260
data = new[len+1];
245261
resp = new[len+1];
246262
for (int beat=0; beat <= len; beat++) begin
247-
get_read_beat(beat_data, beat_resp);
248-
data[beat] = beat_data;
249-
resp[beat] = beat_resp;
263+
get_read_beat(beat_data, beat_user, beat_resp);
264+
data[beat] = beat_data;
265+
resp_user[beat] = beat_user;
266+
resp[beat] = beat_resp;
250267
end
251268
endtask
252269

@@ -255,27 +272,33 @@ interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, paramet
255272
input logic [IW-1:0] id = IW'(0),
256273
input logic lock = 1'b0,
257274
output logic [DW-1:0] data,
275+
output logic [UW-1:0] resp_user,
258276
output axi_resp_e resp);
259277
automatic axi_resp_e burst_resp[];
278+
automatic logic [UW-1:0] burst_ruser[];
260279
automatic logic [DW-1:0] burst_data[];
261-
axi_read(.addr(addr),
262-
.user(user),
263-
.id (id ),
264-
.lock(lock),
265-
.data(burst_data),
266-
.resp(burst_resp));
267-
data = burst_data[0];
268-
resp = burst_resp[0];
280+
axi_read(.addr (addr ),
281+
.user (user ),
282+
.id (id ),
283+
.lock (lock ),
284+
.data (burst_data ),
285+
.resp_user(burst_ruser),
286+
.resp (burst_resp ));
287+
data = burst_data[0];
288+
resp_user = burst_ruser[0];
289+
resp = burst_resp[0];
269290
endtask
270291

271292
task send_write_beat(input logic last,
272293
input logic [DW-1:0] data,
294+
input logic [UW-1:0] user,
273295
input logic [DW/8-1:0] strb);
274296
`TIME_ALGN
275297
wvalid `EQ__ 1;
276298
wlast `EQ__ last;
277299
wdata `EQ__ data;
278300
wstrb `EQ__ strb;
301+
wuser `EQ__ user;
279302
do
280303
@(posedge clk);
281304
while (!wready);
@@ -284,17 +307,20 @@ interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, paramet
284307
wlast `EQ__ '0;
285308
wdata `EQ__ '0;
286309
wstrb `EQ__ '0;
310+
wuser `EQ__ '0;
287311
wait(!wvalid);
288312
endtask
289313

290314
// TODO handle ID
291-
task get_write_resp(output axi_resp_e resp);
315+
task get_write_resp(output axi_resp_e resp,
316+
output logic [UW-1:0] user);
292317
`TIME_ALGN
293318
bready `EQ__ 1;
294319
do
295320
@(posedge clk);
296321
while(!bvalid);
297322
resp `EQ__ axi_resp_e'(bresp);
323+
user `EQ__ buser;
298324
`TIME_ALGN
299325
bready `EQ__ 0;
300326
wait(!bready);
@@ -310,7 +336,10 @@ interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, paramet
310336
input logic [DW-1:0] data [],
311337
input logic use_strb = 0,
312338
input logic [DW/8-1:0] strb [],
313-
output axi_resp_e resp);
339+
input logic use_write_user = 0,
340+
input logic [UW-1:0] write_user [],
341+
output axi_resp_e resp,
342+
output logic [UW-1:0] resp_user);
314343
while(!rst_n) @(posedge clk);
315344
do begin
316345
`TIME_ALGN
@@ -335,8 +364,8 @@ interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, paramet
335364
awvalid `EQ__ '0;
336365
fork
337366
for (int beat=0; beat <= len; beat++)
338-
send_write_beat(beat == len, data[beat], use_strb ? strb[beat] : {DW/8{1'b1}});
339-
get_write_resp(resp);
367+
send_write_beat(beat == len, data[beat], use_write_user ? write_user[beat] : UW'(0), use_strb ? strb[beat] : {DW/8{1'b1}});
368+
get_write_resp(resp, resp_user);
340369
join
341370
endtask
342371

@@ -345,8 +374,11 @@ interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, paramet
345374
input logic [IW-1:0] id = IW'(0),
346375
input logic lock = 1'b0,
347376
input logic [DW-1:0] data,
348-
output axi_resp_e resp);
377+
input logic [UW-1:0] write_user = UW'(0),
378+
output axi_resp_e resp,
379+
output logic [UW-1:0] resp_user);
349380
automatic logic [DW/8-1:0] burst_strb[] = new[1]('{{DW/8{1'b1}}});
381+
automatic logic [UW -1:0] burst_user[] = new[1]('{write_user});
350382
automatic logic [DW -1:0] burst_data[] = new[1]('{data});
351383
axi_write(.addr(addr),
352384
.user(user),
@@ -355,10 +387,15 @@ interface axi_if #(parameter integer AW = 32, parameter integer DW = 32, paramet
355387
.data(burst_data),
356388
.use_strb(0),
357389
.strb(burst_strb),
358-
.resp(resp));
390+
.use_write_user(0),
391+
.write_user(burst_user),
392+
.resp(resp),
393+
.resp_user(resp_user));
359394
endtask
360395

361396
`undef EQ__
362397
`undef TIME_ALGN
363398

399+
// synopsys translate_on
400+
364401
endinterface

‎src/libs/axi/axi_sub.sv‎

Lines changed: 15 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,7 @@ module axi_sub import axi_pkg::*; #(
5757
output logic [IW-1:0] id,
5858
output logic [DW-1:0] wdata, // Requires: Component dwidth == AXI dwidth
5959
output logic [BC-1:0] wstrb, // Requires: Component dwidth == AXI dwidth
60+
output logic [2:0] size,
6061
input logic [DW-1:0] rdata, // Requires: Component dwidth == AXI dwidth
6162
output logic last, // Asserted with final 'dv' of a burst
6263
input logic hld,
@@ -66,18 +67,21 @@ module axi_sub import axi_pkg::*; #(
6667
);
6768

6869
// Exclusive Access Signals
70+
`ifdef CALIPTRA_AXI_SUB_EX_EN
6971
logic [ID_NUM-1:0] ex_clr;
7072
logic [ID_NUM-1:0] ex_active;
7173
struct packed {
7274
logic [AW-1:0] addr;
7375
logic [AW-1:0] addr_mask;
7476
} [ID_NUM-1:0] ex_ctx;
77+
`endif
7578

7679
//Read Subordinate INF
7780
logic r_dv;
7881
logic [AW-1:0] r_addr; // Byte address
7982
logic [UW-1:0] r_user;
8083
logic [IW-1:0] r_id;
84+
logic [2:0] r_size;
8185
logic r_last; // Asserted with final 'dv' of a burst
8286
logic r_hld;
8387
logic r_err;
@@ -91,6 +95,7 @@ module axi_sub import axi_pkg::*; #(
9195
logic [IW-1:0] w_id;
9296
logic [DW-1:0] w_wdata; // Requires: Component dwidth == AXI dwidth
9397
logic [BC-1:0] w_wstrb; // Requires: Component dwidth == AXI dwidth
98+
logic [2:0] w_size;
9499
logic w_last; // Asserted with final 'dv' of a burst
95100
logic w_hld;
96101
logic w_err;
@@ -100,9 +105,8 @@ module axi_sub import axi_pkg::*; #(
100105
.AW (AW ),
101106
.DW (DW ),
102107
.UW (UW ),
103-
.IW (IW ),
108+
.IW (IW )
104109

105-
.EX_EN(EX_EN)
106110
) i_axi_sub_wr (
107111
.clk (clk ),
108112
.rst_n(rst_n),
@@ -111,9 +115,11 @@ module axi_sub import axi_pkg::*; #(
111115
.s_axi_if(s_axi_w_if),
112116

113117
// Exclusive Access Signals
118+
`ifdef CALIPTRA_AXI_SUB_EX_EN
114119
.ex_clr (ex_clr ),
115120
.ex_active(ex_active),
116121
.ex_ctx (ex_ctx ),
122+
`endif
117123

118124
//COMPONENT INF
119125
.dv (w_dv ),
@@ -122,6 +128,7 @@ module axi_sub import axi_pkg::*; #(
122128
.id (w_id ),
123129
.wdata(w_wdata),
124130
.wstrb(w_wstrb),
131+
.wsize(w_size ),
125132
.last (w_last ),
126133
.hld (w_hld ),
127134
.err (w_err )
@@ -134,7 +141,6 @@ module axi_sub import axi_pkg::*; #(
134141
.UW(UW),
135142
.IW(IW),
136143

137-
.EX_EN(EX_EN),
138144
.C_LAT(C_LAT)
139145
) i_axi_sub_rd (
140146
.clk (clk ),
@@ -144,15 +150,18 @@ module axi_sub import axi_pkg::*; #(
144150
.s_axi_if(s_axi_r_if),
145151

146152
// Exclusive Access Signals
153+
`ifdef CALIPTRA_AXI_SUB_EX_EN
147154
.ex_clr (ex_clr ),
148155
.ex_active(ex_active),
149156
.ex_ctx (ex_ctx ),
157+
`endif
150158

151159
//COMPONENT INF
152160
.dv (r_dv ),
153161
.addr (r_addr ),
154162
.user (r_user ),
155163
.id (r_id ),
164+
.size (r_size ),
156165
.last (r_last ),
157166
.hld (r_hld ),
158167
.err (r_err ),
@@ -166,7 +175,6 @@ module axi_sub import axi_pkg::*; #(
166175
.UW(UW),
167176
.IW(IW),
168177

169-
.EX_EN(EX_EN),
170178
.C_LAT(C_LAT)
171179
) i_axi_sub_arb (
172180
.clk (clk ),
@@ -178,6 +186,7 @@ module axi_sub import axi_pkg::*; #(
178186
.r_user (r_user ),
179187
.r_id (r_id ),
180188
.r_last (r_last ),
189+
.r_size (r_size ),
181190
.r_hld (r_hld ),
182191
.r_err (r_err ),
183192
.r_rdata(r_rdata),
@@ -189,6 +198,7 @@ module axi_sub import axi_pkg::*; #(
189198
.w_id (w_id ),
190199
.w_wdata(w_wdata),
191200
.w_wstrb(w_wstrb),
201+
.w_size (w_size ),
192202
.w_last (w_last ),
193203
.w_hld (w_hld ),
194204
.w_err (w_err ),
@@ -201,6 +211,7 @@ module axi_sub import axi_pkg::*; #(
201211
.id (id ),
202212
.wdata (wdata ),
203213
.wstrb (wstrb ),
214+
.size (size ),
204215
.last (last ),
205216
.hld (hld ),
206217
.rd_err (rd_err ),

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