verification: cocotb: Unified convention of tests' naming

Signed-off-by: Grzegorz Latosinski <[email protected]>

Author: glatosinski

verification/cocotb/block/i2c/test_write.py

@@ -61,7 +61,7 @@ async def test_write_sequence(
 
 
 @cocotb.test()
-async def run_test(dut):
+async def test_write(dut):
     TARGET_ADDR = 0x18
     CLK_SPEED = 400e3
 

verification/cocotb/block/i2c_controller_fsm/test_mem_rw.py

@@ -17,7 +17,7 @@
 
 
 @cocotb.test()
-async def run_test(dut):
+async def test_mem_rw(dut):
     """
     Executes random read and writes while checking data on the I2C FSM.
     """

verification/cocotb/block/i2c_standby_controller/test_read.py

@@ -102,7 +102,7 @@ def ord_or_null(idx):
 
 
 @cocotb.test()
-async def run_test(dut):
+async def test_read(dut):
     TARGET_ADDR = 0x18
     CLK_SPEED = 400e3
 

verification/cocotb/block/i2c_standby_controller/test_wr_restart_rd.py

@@ -159,7 +159,7 @@ async def master_write_read():
 
 
 @cocotb.test()
-async def run_test(dut):
+async def test_wr_restart_rd(dut):
     TARGET_ADDR = 12
     CLK_SPEED = 400000
 

verification/cocotb/block/i2c_target_fsm/test_mem_r.py

@@ -75,7 +75,7 @@ async def test_read_sequence(dut: Any, address: int, master: I2cMaster, data: by
 
 
 @cocotb.test()
-async def run_test(dut):
+async def test_mem_r(dut):
     TARGET_ADDR = 12
     CLK_SPEED = 400000
 

verification/cocotb/block/i2c_target_fsm/test_mem_w.py

@@ -48,7 +48,7 @@ def MatchWDataExact(value, dut):
 
 
 @cocotb.test()
-async def run_test(dut):
+async def test_mem_w(dut):
     TARGET_ADDR = 12
     CLK_SPEED = 400000
 

verification/cocotb/block/lib_adapter/test_csr_sw_access.py

@@ -65,7 +65,7 @@ async def write_csr_and_verify(
 
 # Common test cases for frontend adapters:
 @cocotb.test()
-async def run_read_hci_version_csr(dut: SimHandleBase):
+async def test_read_hci_version_csr(dut: SimHandleBase):
     """Run test to read HCI version register."""
 
     tb = get_frontend_bus_if()(dut)
@@ -78,7 +78,7 @@ async def run_read_hci_version_csr(dut: SimHandleBase):
 
 
 @cocotb.test()
-async def run_read_pio_section_offset(dut: SimHandleBase):
+async def test_read_pio_section_offset(dut: SimHandleBase):
     """Run test to read PIO section offset register."""
 
     tb = get_frontend_bus_if()(dut)
@@ -88,7 +88,7 @@ async def run_read_pio_section_offset(dut: SimHandleBase):
 
 
 @cocotb.test()
-async def run_write_to_controller_device_addr(dut: SimHandleBase):
+async def test_write_to_controller_device_addr(dut: SimHandleBase):
     """Run test to write & read from Controller Device Address."""
 
     tb = get_frontend_bus_if()(dut)
@@ -102,7 +102,7 @@ async def run_write_to_controller_device_addr(dut: SimHandleBase):
 
 
 @cocotb.test()
-async def run_write_should_not_affect_ro_csr(dut: SimHandleBase):
+async def test_write_should_not_affect_ro_csr(dut: SimHandleBase):
     """Run test to write to RO HC Capabilities."""
 
     tb = get_frontend_bus_if()(dut)
@@ -118,7 +118,7 @@ async def run_write_should_not_affect_ro_csr(dut: SimHandleBase):
 
 
 @cocotb.test()
-async def run_sequence_csr_read(dut: SimHandleBase):
+async def test_sequence_csr_read(dut: SimHandleBase):
     tb = get_frontend_bus_if()(dut)
     await tb.register_test_interfaces()
 
@@ -152,7 +152,7 @@ async def run_sequence_csr_read(dut: SimHandleBase):
 
 
 @cocotb.test()
-async def run_sequence_csr_write(dut: SimHandleBase):
+async def test_sequence_csr_write(dut: SimHandleBase):
     tb = get_frontend_bus_if()(dut)
     await tb.register_test_interfaces()
 

verification/cocotb/block/lib_hci_queues/test_clear.py

@@ -11,7 +11,7 @@
 
 
 @cocotb.test()
-async def run_clear_on_nonempty_resp_queue(dut: SimHandleBase):
+async def test_clear_on_nonempty_resp_queue(dut: SimHandleBase):
     """
     Issue Response queue clear through RESET_CONTROL and verify the newly enqueued
     response will be returned on the read
@@ -39,7 +39,7 @@ async def run_clear_on_nonempty_resp_queue(dut: SimHandleBase):
 
 
 @cocotb.test()
-async def run_clear_on_nonempty_cmd_queue(dut: SimHandleBase):
+async def test_clear_on_nonempty_cmd_queue(dut: SimHandleBase):
     """
     Issue Command queue clear through RESET_CONTROL and verify the newly enqueued
     command will be returned on the read
@@ -66,7 +66,7 @@ async def run_clear_on_nonempty_cmd_queue(dut: SimHandleBase):
 
 
 @cocotb.test()
-async def run_clear_on_nonempty_rx_queue(dut: SimHandleBase):
+async def test_clear_on_nonempty_rx_queue(dut: SimHandleBase):
     """
     Issue RX queue clear through RESET_CONTROL and verify the newly enqueued
     data will be returned on the read
@@ -91,7 +91,7 @@ async def run_clear_on_nonempty_rx_queue(dut: SimHandleBase):
 
 
 @cocotb.test()
-async def run_clear_on_nonempty_tx_queue(dut: SimHandleBase):
+async def test_clear_on_nonempty_tx_queue(dut: SimHandleBase):
     """
     Issue TX queue clear through RESET_CONTROL and verify the newly enqueued
     data will be returned on the read
@@ -116,7 +116,7 @@ async def run_clear_on_nonempty_tx_queue(dut: SimHandleBase):
 
 
 @cocotb.test()
-async def run_clear_on_nonempty_ibi_queue(dut: SimHandleBase):
+async def test_clear_on_nonempty_ibi_queue(dut: SimHandleBase):
     """
     Issue IBI queue clear through RESET_CONTROL and verify the newly enqueued
     data will be returned on the read

verification/cocotb/block/lib_hci_queues/test_empty.py

@@ -20,50 +20,50 @@ async def should_be_empty_after_rst(dut: SimHandleBase, if_name: str, queue: str
 
 
 @cocotb.test()
-async def run_cmd_capacity_status_test(dut: SimHandleBase):
+async def test_cmd_capacity_status(dut: SimHandleBase):
     await should_be_empty_after_rst(dut, "hci", "cmd")
 
 
 @cocotb.test()
-async def run_rx_capacity_status_test(dut: SimHandleBase):
+async def test_rx_capacity_status(dut: SimHandleBase):
     await should_be_empty_after_rst(dut, "hci", "rx")
 
 
 @cocotb.test()
-async def run_resp_capacity_status_test(dut: SimHandleBase):
+async def test_resp_capacity_status(dut: SimHandleBase):
     await should_be_empty_after_rst(dut, "hci", "resp")
 
 
 @cocotb.test()
-async def run_tx_capacity_status_test(dut: SimHandleBase):
+async def test_tx_capacity_status(dut: SimHandleBase):
     await should_be_empty_after_rst(dut, "hci", "tx")
 
 
 @cocotb.test()
-async def run_ibi_capacity_status_test(dut: SimHandleBase):
+async def test_ibi_capacity_status(dut: SimHandleBase):
     await should_be_empty_after_rst(dut, "hci", "ibi")
 
 
 @cocotb.test()
-async def run_tti_tx_desc_capacity_status_test(dut: SimHandleBase):
+async def test_tti_tx_desc_capacity_status(dut: SimHandleBase):
     await should_be_empty_after_rst(dut, "tti", "tx_desc")
 
 
 @cocotb.test()
-async def run_tti_rx_capacity_status_test(dut: SimHandleBase):
+async def test_tti_rx_capacity_status(dut: SimHandleBase):
     await should_be_empty_after_rst(dut, "tti", "rx")
 
 
 @cocotb.test()
-async def run_tti_rx_desc_capacity_status_test(dut: SimHandleBase):
+async def test_tti_rx_desc_capacity_status(dut: SimHandleBase):
     await should_be_empty_after_rst(dut, "tti", "rx_desc")
 
 
 @cocotb.test()
-async def run_tti_tx_capacity_status_test(dut: SimHandleBase):
+async def test_tti_tx_capacity_status(dut: SimHandleBase):
     await should_be_empty_after_rst(dut, "tti", "tx")
 
 
 @cocotb.test()
-async def run_tti_ibi_capacity_status_test(dut: SimHandleBase):
+async def test_tti_ibi_capacity_status(dut: SimHandleBase):
     await should_be_empty_after_rst(dut, "tti", "ibi")

verification/cocotb/block/lib_hci_queues/test_threshold.py

@@ -417,67 +417,67 @@ async def should_setup_ready_threshold(interface: HCIBaseTestInterface, q: Queue
 
 
 @cocotb.test()
-async def run_cmd_setup_threshold_test(dut: SimHandleBase):
+async def test_cmd_setup_threshold(dut: SimHandleBase):
     interface = await setup_sim(dut, "hci")
     await should_setup_ready_threshold(interface, CmdQueueThldHandler())
 
 
 @cocotb.test()
-async def run_rx_setup_threshold_test(dut: SimHandleBase):
+async def test_rx_setup_threshold(dut: SimHandleBase):
     interface = await setup_sim(dut, "hci")
     await should_setup_start_threshold(interface, RxQueueThldHandler())
     await should_setup_ready_threshold(interface, RxQueueThldHandler())
 
 
 @cocotb.test()
-async def run_tx_setup_threshold_test(dut: SimHandleBase):
+async def test_tx_setup_threshold(dut: SimHandleBase):
     interface = await setup_sim(dut, "hci")
     await should_setup_start_threshold(interface, TxQueueThldHandler())
     await should_setup_ready_threshold(interface, TxQueueThldHandler())
 
 
 @cocotb.test()
-async def run_resp_setup_threshold_test(dut: SimHandleBase):
+async def test_resp_setup_threshold(dut: SimHandleBase):
     interface = await setup_sim(dut, "hci")
     await should_setup_ready_threshold(interface, RespQueueThldHandler())
 
 
 @cocotb.test()
-async def run_ibi_setup_threshold_test(dut: SimHandleBase):
+async def test_ibi_setup_threshold(dut: SimHandleBase):
     interface = await setup_sim(dut, "hci")
     await should_setup_ready_threshold(interface, IbiQueueThldHandler())
 
 
 @cocotb.test()
-async def run_tti_tx_desc_setup_threshold_test(dut: SimHandleBase):
+async def test_tti_tx_desc_setup_threshold(dut: SimHandleBase):
     interface = await setup_sim(dut, "tti")
     await should_setup_ready_threshold(interface, TTITxDescQueueThldHandler())
 
 
 @cocotb.test()
-async def run_tti_rx_setup_threshold_test(dut: SimHandleBase):
+async def test_tti_rx_setup_threshold(dut: SimHandleBase):
     interface = await setup_sim(dut, "tti")
     # TODO: Enable start threshold test once it's added to the design
     # await should_setup_start_threshold(interface, TTIRxQueueThldHandler())
     await should_setup_ready_threshold(interface, TTIRxQueueThldHandler())
 
 
 @cocotb.test()
-async def run_tti_tx_setup_threshold_test(dut: SimHandleBase):
+async def test_tti_tx_setup_threshold(dut: SimHandleBase):
     interface = await setup_sim(dut, "tti")
     # TODO: Enable start threshold test once it's added to the design
     # await should_setup_start_threshold(interface, TTITxQueueThldHandler())
     await should_setup_ready_threshold(interface, TTITxQueueThldHandler())
 
 
 @cocotb.test()
-async def run_tti_rx_desc_setup_threshold_test(dut: SimHandleBase):
+async def test_tti_rx_desc_setup_threshold(dut: SimHandleBase):
     interface = await setup_sim(dut, "tti")
     await should_setup_ready_threshold(interface, TTIRxDescQueueThldHandler())
 
 
 @cocotb.test()
-async def run_tti_ibi_setup_threshold_test(dut: SimHandleBase):
+async def test_tti_ibi_setup_threshold(dut: SimHandleBase):
     interface = await setup_sim(dut, "tti")
     await should_setup_ready_threshold(interface, TtiIbiQueueThldHandler())
 
@@ -596,32 +596,32 @@ async def should_raise_ready_thld_trig_receiver(
 
 
 @cocotb.test()
-async def run_resp_should_raise_thld_trig_test(dut: SimHandleBase):
+async def test_resp_should_raise_thld_trig(dut: SimHandleBase):
     interface = await setup_sim(dut, "hci")
     await should_raise_ready_thld_trig_receiver(interface, RespQueueThldHandler())
 
 
 @cocotb.test()
-async def run_rx_should_raise_thld_trig_test(dut: SimHandleBase):
+async def test_rx_should_raise_thld_trig(dut: SimHandleBase):
     interface = await setup_sim(dut, "hci")
     await should_raise_start_thld_trig_receiver(interface, RxQueueThldHandler())
     await should_raise_ready_thld_trig_receiver(interface, RxQueueThldHandler())
 
 
 @cocotb.test()
-async def run_ibi_should_raise_thld_trig_test(dut: SimHandleBase):
+async def test_ibi_should_raise_thld_trig(dut: SimHandleBase):
     interface = await setup_sim(dut, "hci")
     await should_raise_ready_thld_trig_receiver(interface, IbiQueueThldHandler())
 
 
 @cocotb.test()
-async def run_tti_rx_desc_should_raise_thld_trig_test(dut: SimHandleBase):
+async def test_tti_rx_desc_should_raise_thld_trig(dut: SimHandleBase):
     interface = await setup_sim(dut, "tti")
     await should_raise_ready_thld_trig_receiver(interface, TTIRxDescQueueThldHandler())
 
 
 @cocotb.test()
-async def run_tti_rx_should_raise_thld_trig_test(dut: SimHandleBase):
+async def test_tti_rx_should_raise_thld_trig(dut: SimHandleBase):
     interface = await setup_sim(dut, "tti")
     # TODO: Enable start threshold test once it's added to the design
     await should_raise_start_thld_trig_receiver(interface, TTIRxQueueThldHandler())
@@ -745,20 +745,20 @@ async def should_raise_ready_thld_trig_transmitter(
 
 
 @cocotb.test()
-async def run_cmd_should_raise_thld_trig_test(dut: SimHandleBase):
+async def test_cmd_should_raise_thld_trig(dut: SimHandleBase):
     interface = await setup_sim(dut, "hci")
     await should_raise_ready_thld_trig_transmitter(interface, CmdQueueThldHandler())
 
 
 @cocotb.test()
-async def run_tx_should_raise_thld_trig_test(dut: SimHandleBase):
+async def test_tx_should_raise_thld_trig(dut: SimHandleBase):
     interface = await setup_sim(dut, "hci")
     await should_raise_start_thld_trig_transmitter(interface, TxQueueThldHandler())
     await should_raise_ready_thld_trig_transmitter(interface, TxQueueThldHandler())
 
 
 @cocotb.test()
-async def run_tti_tx_desc_should_raise_thld_trig_test(dut: SimHandleBase):
+async def test_tti_tx_desc_should_raise_thld_trig(dut: SimHandleBase):
     interface = await setup_sim(dut, "tti")
     await should_raise_ready_thld_trig_transmitter(interface, TTITxDescQueueThldHandler())
 
@@ -768,14 +768,14 @@ async def run_tti_tx_desc_should_raise_thld_trig_test(dut: SimHandleBase):
 # falls through it hence is not accounted by the threshold counter. Fixing this
 # requires reworking the converter itself or the queue - converter interface.
 @cocotb.test(skip=True)
-async def run_tti_tx_should_raise_thld_trig_test(dut: SimHandleBase):
+async def test_tti_tx_should_raise_thld_trig(dut: SimHandleBase):
     interface = await setup_sim(dut, "tti")
     # TODO: Enable start threshold test once it's added to the design
     await should_raise_start_thld_trig_transmitter(interface, TTITxQueueThldHandler())
     await should_raise_ready_thld_trig_transmitter(interface, TTITxQueueThldHandler())
 
 
 @cocotb.test()
-async def run_tti_ibi_should_raise_thld_trig_test(dut: SimHandleBase):
+async def test_tti_ibi_should_raise_thld_trig(dut: SimHandleBase):
     interface = await setup_sim(dut, "tti")
     await should_raise_ready_thld_trig_transmitter(interface, TtiIbiQueueThldHandler())