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kgugalakgugala
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target: refactor TX_DESC interrupts
TX_DESC_STAT is now toggled on private read start. Added TX_DESC_COMPLETE, triggered when private read is completed. Signed-off-by: Karol Gugala <[email protected]>
1 parent c01c2c7 commit 76e5486

15 files changed

+280
-29
lines changed

‎src/csr/I3CCSR.sv‎

Lines changed: 99 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1425,6 +1425,10 @@ module I3CCSR (
14251425
logic next;
14261426
logic load_next;
14271427
} TRANSFER_ABORT_STAT;
1428+
struct packed{
1429+
logic next;
1430+
logic load_next;
1431+
} TX_DESC_COMPLETE;
14281432
struct packed{
14291433
logic next;
14301434
logic load_next;
@@ -1475,6 +1479,10 @@ module I3CCSR (
14751479
logic next;
14761480
logic load_next;
14771481
} TRANSFER_ABORT_STAT_EN;
1482+
struct packed{
1483+
logic next;
1484+
logic load_next;
1485+
} TX_DESC_COMPLETE_EN;
14781486
struct packed{
14791487
logic next;
14801488
logic load_next;
@@ -1525,6 +1533,10 @@ module I3CCSR (
15251533
logic next;
15261534
logic load_next;
15271535
} TRANSFER_ABORT_STAT_FORCE;
1536+
struct packed{
1537+
logic next;
1538+
logic load_next;
1539+
} TX_DESC_COMPLETE_FORCE;
15281540
struct packed{
15291541
logic next;
15301542
logic load_next;
@@ -2554,6 +2566,9 @@ module I3CCSR (
25542566
struct packed{
25552567
logic value;
25562568
} TRANSFER_ABORT_STAT;
2569+
struct packed{
2570+
logic value;
2571+
} TX_DESC_COMPLETE;
25572572
struct packed{
25582573
logic value;
25592574
} TRANSFER_ERR_STAT;
@@ -2592,6 +2607,9 @@ module I3CCSR (
25922607
struct packed{
25932608
logic value;
25942609
} TRANSFER_ABORT_STAT_EN;
2610+
struct packed{
2611+
logic value;
2612+
} TX_DESC_COMPLETE_EN;
25952613
struct packed{
25962614
logic value;
25972615
} TRANSFER_ERR_STAT_EN;
@@ -2630,6 +2648,9 @@ module I3CCSR (
26302648
struct packed{
26312649
logic value;
26322650
} TRANSFER_ABORT_STAT_FORCE;
2651+
struct packed{
2652+
logic value;
2653+
} TX_DESC_COMPLETE_FORCE;
26332654
struct packed{
26342655
logic value;
26352656
} TRANSFER_ERR_STAT_FORCE;
@@ -8321,6 +8342,32 @@ module I3CCSR (
83218342
end
83228343
end
83238344
assign hwif_out.I3C_EC.TTI.INTERRUPT_STATUS.TRANSFER_ABORT_STAT.value = field_storage.I3C_EC.TTI.INTERRUPT_STATUS.TRANSFER_ABORT_STAT.value;
8345+
// Field: I3CCSR.I3C_EC.TTI.INTERRUPT_STATUS.TX_DESC_COMPLETE
8346+
always_comb begin
8347+
automatic logic [0:0] next_c;
8348+
automatic logic load_next_c;
8349+
next_c = field_storage.I3C_EC.TTI.INTERRUPT_STATUS.TX_DESC_COMPLETE.value;
8350+
load_next_c = '0;
8351+
if(decoded_reg_strb.I3C_EC.TTI.INTERRUPT_STATUS && decoded_req_is_wr) begin // SW write 1 clear
8352+
next_c = field_storage.I3C_EC.TTI.INTERRUPT_STATUS.TX_DESC_COMPLETE.value & ~(decoded_wr_data[26:26] & decoded_wr_biten[26:26]);
8353+
load_next_c = '1;
8354+
end else if(hwif_in.I3C_EC.TTI.INTERRUPT_STATUS.TX_DESC_COMPLETE.we) begin // HW Write - we
8355+
next_c = hwif_in.I3C_EC.TTI.INTERRUPT_STATUS.TX_DESC_COMPLETE.next;
8356+
load_next_c = '1;
8357+
end
8358+
field_combo.I3C_EC.TTI.INTERRUPT_STATUS.TX_DESC_COMPLETE.next = next_c;
8359+
field_combo.I3C_EC.TTI.INTERRUPT_STATUS.TX_DESC_COMPLETE.load_next = load_next_c;
8360+
end
8361+
always_ff @(posedge clk or negedge hwif_in.rst_ni) begin
8362+
if(~hwif_in.rst_ni) begin
8363+
field_storage.I3C_EC.TTI.INTERRUPT_STATUS.TX_DESC_COMPLETE.value <= 1'h0;
8364+
end else begin
8365+
if(field_combo.I3C_EC.TTI.INTERRUPT_STATUS.TX_DESC_COMPLETE.load_next) begin
8366+
field_storage.I3C_EC.TTI.INTERRUPT_STATUS.TX_DESC_COMPLETE.value <= field_combo.I3C_EC.TTI.INTERRUPT_STATUS.TX_DESC_COMPLETE.next;
8367+
end
8368+
end
8369+
end
8370+
assign hwif_out.I3C_EC.TTI.INTERRUPT_STATUS.TX_DESC_COMPLETE.value = field_storage.I3C_EC.TTI.INTERRUPT_STATUS.TX_DESC_COMPLETE.value;
83248371
// Field: I3CCSR.I3C_EC.TTI.INTERRUPT_STATUS.TRANSFER_ERR_STAT
83258372
always_comb begin
83268373
automatic logic [0:0] next_c;
@@ -8600,6 +8647,29 @@ module I3CCSR (
86008647
end
86018648
end
86028649
assign hwif_out.I3C_EC.TTI.INTERRUPT_ENABLE.TRANSFER_ABORT_STAT_EN.value = field_storage.I3C_EC.TTI.INTERRUPT_ENABLE.TRANSFER_ABORT_STAT_EN.value;
8650+
// Field: I3CCSR.I3C_EC.TTI.INTERRUPT_ENABLE.TX_DESC_COMPLETE_EN
8651+
always_comb begin
8652+
automatic logic [0:0] next_c;
8653+
automatic logic load_next_c;
8654+
next_c = field_storage.I3C_EC.TTI.INTERRUPT_ENABLE.TX_DESC_COMPLETE_EN.value;
8655+
load_next_c = '0;
8656+
if(decoded_reg_strb.I3C_EC.TTI.INTERRUPT_ENABLE && decoded_req_is_wr) begin // SW write
8657+
next_c = (field_storage.I3C_EC.TTI.INTERRUPT_ENABLE.TX_DESC_COMPLETE_EN.value & ~decoded_wr_biten[26:26]) | (decoded_wr_data[26:26] & decoded_wr_biten[26:26]);
8658+
load_next_c = '1;
8659+
end
8660+
field_combo.I3C_EC.TTI.INTERRUPT_ENABLE.TX_DESC_COMPLETE_EN.next = next_c;
8661+
field_combo.I3C_EC.TTI.INTERRUPT_ENABLE.TX_DESC_COMPLETE_EN.load_next = load_next_c;
8662+
end
8663+
always_ff @(posedge clk or negedge hwif_in.rst_ni) begin
8664+
if(~hwif_in.rst_ni) begin
8665+
field_storage.I3C_EC.TTI.INTERRUPT_ENABLE.TX_DESC_COMPLETE_EN.value <= 1'h0;
8666+
end else begin
8667+
if(field_combo.I3C_EC.TTI.INTERRUPT_ENABLE.TX_DESC_COMPLETE_EN.load_next) begin
8668+
field_storage.I3C_EC.TTI.INTERRUPT_ENABLE.TX_DESC_COMPLETE_EN.value <= field_combo.I3C_EC.TTI.INTERRUPT_ENABLE.TX_DESC_COMPLETE_EN.next;
8669+
end
8670+
end
8671+
end
8672+
assign hwif_out.I3C_EC.TTI.INTERRUPT_ENABLE.TX_DESC_COMPLETE_EN.value = field_storage.I3C_EC.TTI.INTERRUPT_ENABLE.TX_DESC_COMPLETE_EN.value;
86038673
// Field: I3CCSR.I3C_EC.TTI.INTERRUPT_ENABLE.TRANSFER_ERR_STAT_EN
86048674
always_comb begin
86058675
automatic logic [0:0] next_c;
@@ -8876,6 +8946,29 @@ module I3CCSR (
88768946
end
88778947
end
88788948
assign hwif_out.I3C_EC.TTI.INTERRUPT_FORCE.TRANSFER_ABORT_STAT_FORCE.value = field_storage.I3C_EC.TTI.INTERRUPT_FORCE.TRANSFER_ABORT_STAT_FORCE.value;
8949+
// Field: I3CCSR.I3C_EC.TTI.INTERRUPT_FORCE.TX_DESC_COMPLETE_FORCE
8950+
always_comb begin
8951+
automatic logic [0:0] next_c;
8952+
automatic logic load_next_c;
8953+
next_c = field_storage.I3C_EC.TTI.INTERRUPT_FORCE.TX_DESC_COMPLETE_FORCE.value;
8954+
load_next_c = '0;
8955+
if(decoded_reg_strb.I3C_EC.TTI.INTERRUPT_FORCE && decoded_req_is_wr) begin // SW write
8956+
next_c = (field_storage.I3C_EC.TTI.INTERRUPT_FORCE.TX_DESC_COMPLETE_FORCE.value & ~decoded_wr_biten[26:26]) | (decoded_wr_data[26:26] & decoded_wr_biten[26:26]);
8957+
load_next_c = '1;
8958+
end
8959+
field_combo.I3C_EC.TTI.INTERRUPT_FORCE.TX_DESC_COMPLETE_FORCE.next = next_c;
8960+
field_combo.I3C_EC.TTI.INTERRUPT_FORCE.TX_DESC_COMPLETE_FORCE.load_next = load_next_c;
8961+
end
8962+
always_ff @(posedge clk or negedge hwif_in.rst_ni) begin
8963+
if(~hwif_in.rst_ni) begin
8964+
field_storage.I3C_EC.TTI.INTERRUPT_FORCE.TX_DESC_COMPLETE_FORCE.value <= 1'h0;
8965+
end else begin
8966+
if(field_combo.I3C_EC.TTI.INTERRUPT_FORCE.TX_DESC_COMPLETE_FORCE.load_next) begin
8967+
field_storage.I3C_EC.TTI.INTERRUPT_FORCE.TX_DESC_COMPLETE_FORCE.value <= field_combo.I3C_EC.TTI.INTERRUPT_FORCE.TX_DESC_COMPLETE_FORCE.next;
8968+
end
8969+
end
8970+
end
8971+
assign hwif_out.I3C_EC.TTI.INTERRUPT_FORCE.TX_DESC_COMPLETE_FORCE.value = field_storage.I3C_EC.TTI.INTERRUPT_FORCE.TX_DESC_COMPLETE_FORCE.value;
88798972
// Field: I3CCSR.I3C_EC.TTI.INTERRUPT_FORCE.TRANSFER_ERR_STAT_FORCE
88808973
always_comb begin
88818974
automatic logic [0:0] next_c;
@@ -10261,7 +10354,8 @@ module I3CCSR (
1026110354
assign readback_array[78][18:15] = (decoded_reg_strb.I3C_EC.TTI.INTERRUPT_STATUS && !decoded_req_is_wr) ? field_storage.I3C_EC.TTI.INTERRUPT_STATUS.PENDING_INTERRUPT.value : '0;
1026210355
assign readback_array[78][24:19] = '0;
1026310356
assign readback_array[78][25:25] = (decoded_reg_strb.I3C_EC.TTI.INTERRUPT_STATUS && !decoded_req_is_wr) ? field_storage.I3C_EC.TTI.INTERRUPT_STATUS.TRANSFER_ABORT_STAT.value : '0;
10264-
assign readback_array[78][30:26] = '0;
10357+
assign readback_array[78][26:26] = (decoded_reg_strb.I3C_EC.TTI.INTERRUPT_STATUS && !decoded_req_is_wr) ? field_storage.I3C_EC.TTI.INTERRUPT_STATUS.TX_DESC_COMPLETE.value : '0;
10358+
assign readback_array[78][30:27] = '0;
1026510359
assign readback_array[78][31:31] = (decoded_reg_strb.I3C_EC.TTI.INTERRUPT_STATUS && !decoded_req_is_wr) ? field_storage.I3C_EC.TTI.INTERRUPT_STATUS.TRANSFER_ERR_STAT.value : '0;
1026610360
assign readback_array[79][0:0] = (decoded_reg_strb.I3C_EC.TTI.INTERRUPT_ENABLE && !decoded_req_is_wr) ? field_storage.I3C_EC.TTI.INTERRUPT_ENABLE.RX_DESC_STAT_EN.value : '0;
1026710361
assign readback_array[79][1:1] = (decoded_reg_strb.I3C_EC.TTI.INTERRUPT_ENABLE && !decoded_req_is_wr) ? field_storage.I3C_EC.TTI.INTERRUPT_ENABLE.TX_DESC_STAT_EN.value : '0;
@@ -10276,7 +10370,8 @@ module I3CCSR (
1027610370
assign readback_array[79][13:13] = (decoded_reg_strb.I3C_EC.TTI.INTERRUPT_ENABLE && !decoded_req_is_wr) ? field_storage.I3C_EC.TTI.INTERRUPT_ENABLE.IBI_DONE_EN.value : '0;
1027710371
assign readback_array[79][24:14] = '0;
1027810372
assign readback_array[79][25:25] = (decoded_reg_strb.I3C_EC.TTI.INTERRUPT_ENABLE && !decoded_req_is_wr) ? field_storage.I3C_EC.TTI.INTERRUPT_ENABLE.TRANSFER_ABORT_STAT_EN.value : '0;
10279-
assign readback_array[79][30:26] = '0;
10373+
assign readback_array[79][26:26] = (decoded_reg_strb.I3C_EC.TTI.INTERRUPT_ENABLE && !decoded_req_is_wr) ? field_storage.I3C_EC.TTI.INTERRUPT_ENABLE.TX_DESC_COMPLETE_EN.value : '0;
10374+
assign readback_array[79][30:27] = '0;
1028010375
assign readback_array[79][31:31] = (decoded_reg_strb.I3C_EC.TTI.INTERRUPT_ENABLE && !decoded_req_is_wr) ? field_storage.I3C_EC.TTI.INTERRUPT_ENABLE.TRANSFER_ERR_STAT_EN.value : '0;
1028110376
assign readback_array[80][0:0] = (decoded_reg_strb.I3C_EC.TTI.INTERRUPT_FORCE && !decoded_req_is_wr) ? field_storage.I3C_EC.TTI.INTERRUPT_FORCE.RX_DESC_STAT_FORCE.value : '0;
1028210377
assign readback_array[80][1:1] = (decoded_reg_strb.I3C_EC.TTI.INTERRUPT_FORCE && !decoded_req_is_wr) ? field_storage.I3C_EC.TTI.INTERRUPT_FORCE.TX_DESC_STAT_FORCE.value : '0;
@@ -10291,7 +10386,8 @@ module I3CCSR (
1029110386
assign readback_array[80][13:13] = (decoded_reg_strb.I3C_EC.TTI.INTERRUPT_FORCE && !decoded_req_is_wr) ? field_storage.I3C_EC.TTI.INTERRUPT_FORCE.IBI_DONE_FORCE.value : '0;
1029210387
assign readback_array[80][24:14] = '0;
1029310388
assign readback_array[80][25:25] = (decoded_reg_strb.I3C_EC.TTI.INTERRUPT_FORCE && !decoded_req_is_wr) ? field_storage.I3C_EC.TTI.INTERRUPT_FORCE.TRANSFER_ABORT_STAT_FORCE.value : '0;
10294-
assign readback_array[80][30:26] = '0;
10389+
assign readback_array[80][26:26] = (decoded_reg_strb.I3C_EC.TTI.INTERRUPT_FORCE && !decoded_req_is_wr) ? field_storage.I3C_EC.TTI.INTERRUPT_FORCE.TX_DESC_COMPLETE_FORCE.value : '0;
10390+
assign readback_array[80][30:27] = '0;
1029510391
assign readback_array[80][31:31] = (decoded_reg_strb.I3C_EC.TTI.INTERRUPT_FORCE && !decoded_req_is_wr) ? field_storage.I3C_EC.TTI.INTERRUPT_FORCE.TRANSFER_ERR_STAT_FORCE.value : '0;
1029610392
assign readback_array[81] = hwif_in.I3C_EC.TTI.RX_DESC_QUEUE_PORT.rd_ack ? hwif_in.I3C_EC.TTI.RX_DESC_QUEUE_PORT.rd_data : '0;
1029710393
assign readback_array[82] = hwif_in.I3C_EC.TTI.RX_DATA_PORT.rd_ack ? hwif_in.I3C_EC.TTI.RX_DATA_PORT.rd_data : '0;

‎src/csr/I3CCSR_covergroups.svh‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2062,6 +2062,7 @@
20622062
input bit [1-1:0] IBI_DONE,
20632063
input bit [4-1:0] PENDING_INTERRUPT,
20642064
input bit [1-1:0] TRANSFER_ABORT_STAT,
2065+
input bit [1-1:0] TX_DESC_COMPLETE,
20652066
input bit [1-1:0] TRANSFER_ERR_STAT
20662067
);
20672068
option.per_instance = 1;
@@ -2077,6 +2078,7 @@
20772078
IBI_DONE_cp : coverpoint IBI_DONE;
20782079
PENDING_INTERRUPT_cp : coverpoint PENDING_INTERRUPT;
20792080
TRANSFER_ABORT_STAT_cp : coverpoint TRANSFER_ABORT_STAT;
2081+
TX_DESC_COMPLETE_cp : coverpoint TX_DESC_COMPLETE;
20802082
TRANSFER_ERR_STAT_cp : coverpoint TRANSFER_ERR_STAT;
20812083

20822084
endgroup
@@ -2105,6 +2107,7 @@
21052107
input bit [1-1:0] IBI_THLD_STAT_EN,
21062108
input bit [1-1:0] IBI_DONE_EN,
21072109
input bit [1-1:0] TRANSFER_ABORT_STAT_EN,
2110+
input bit [1-1:0] TX_DESC_COMPLETE_EN,
21082111
input bit [1-1:0] TRANSFER_ERR_STAT_EN
21092112
);
21102113
option.per_instance = 1;
@@ -2119,6 +2122,7 @@
21192122
IBI_THLD_STAT_EN_cp : coverpoint IBI_THLD_STAT_EN;
21202123
IBI_DONE_EN_cp : coverpoint IBI_DONE_EN;
21212124
TRANSFER_ABORT_STAT_EN_cp : coverpoint TRANSFER_ABORT_STAT_EN;
2125+
TX_DESC_COMPLETE_EN_cp : coverpoint TX_DESC_COMPLETE_EN;
21222126
TRANSFER_ERR_STAT_EN_cp : coverpoint TRANSFER_ERR_STAT_EN;
21232127

21242128
endgroup
@@ -2147,6 +2151,7 @@
21472151
input bit [1-1:0] IBI_THLD_FORCE,
21482152
input bit [1-1:0] IBI_DONE_FORCE,
21492153
input bit [1-1:0] TRANSFER_ABORT_STAT_FORCE,
2154+
input bit [1-1:0] TX_DESC_COMPLETE_FORCE,
21502155
input bit [1-1:0] TRANSFER_ERR_STAT_FORCE
21512156
);
21522157
option.per_instance = 1;
@@ -2161,6 +2166,7 @@
21612166
IBI_THLD_FORCE_cp : coverpoint IBI_THLD_FORCE;
21622167
IBI_DONE_FORCE_cp : coverpoint IBI_DONE_FORCE;
21632168
TRANSFER_ABORT_STAT_FORCE_cp : coverpoint TRANSFER_ABORT_STAT_FORCE;
2169+
TX_DESC_COMPLETE_FORCE_cp : coverpoint TX_DESC_COMPLETE_FORCE;
21642170
TRANSFER_ERR_STAT_FORCE_cp : coverpoint TRANSFER_ERR_STAT_FORCE;
21652171

21662172
endgroup

‎src/csr/I3CCSR_pkg.sv‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1140,6 +1140,11 @@ package I3CCSR_pkg;
11401140
logic we;
11411141
} I3CCSR__I3C_EC__TTI__INTERRUPT_STATUS__TRANSFER_ABORT_STAT__in_t;
11421142

1143+
typedef struct packed{
1144+
logic next;
1145+
logic we;
1146+
} I3CCSR__I3C_EC__TTI__INTERRUPT_STATUS__TX_DESC_COMPLETE__in_t;
1147+
11431148
typedef struct packed{
11441149
logic next;
11451150
logic we;
@@ -1158,6 +1163,7 @@ package I3CCSR_pkg;
11581163
I3CCSR__I3C_EC__TTI__INTERRUPT_STATUS__IBI_DONE__in_t IBI_DONE;
11591164
I3CCSR__I3C_EC__TTI__INTERRUPT_STATUS__PENDING_INTERRUPT__in_t PENDING_INTERRUPT;
11601165
I3CCSR__I3C_EC__TTI__INTERRUPT_STATUS__TRANSFER_ABORT_STAT__in_t TRANSFER_ABORT_STAT;
1166+
I3CCSR__I3C_EC__TTI__INTERRUPT_STATUS__TX_DESC_COMPLETE__in_t TX_DESC_COMPLETE;
11611167
I3CCSR__I3C_EC__TTI__INTERRUPT_STATUS__TRANSFER_ERR_STAT__in_t TRANSFER_ERR_STAT;
11621168
} I3CCSR__I3C_EC__TTI__INTERRUPT_STATUS__in_t;
11631169

@@ -2651,6 +2657,10 @@ package I3CCSR_pkg;
26512657
logic value;
26522658
} I3CCSR__I3C_EC__TTI__INTERRUPT_STATUS__TRANSFER_ABORT_STAT__out_t;
26532659

2660+
typedef struct packed{
2661+
logic value;
2662+
} I3CCSR__I3C_EC__TTI__INTERRUPT_STATUS__TX_DESC_COMPLETE__out_t;
2663+
26542664
typedef struct packed{
26552665
logic value;
26562666
} I3CCSR__I3C_EC__TTI__INTERRUPT_STATUS__TRANSFER_ERR_STAT__out_t;
@@ -2668,6 +2678,7 @@ package I3CCSR_pkg;
26682678
I3CCSR__I3C_EC__TTI__INTERRUPT_STATUS__IBI_DONE__out_t IBI_DONE;
26692679
I3CCSR__I3C_EC__TTI__INTERRUPT_STATUS__PENDING_INTERRUPT__out_t PENDING_INTERRUPT;
26702680
I3CCSR__I3C_EC__TTI__INTERRUPT_STATUS__TRANSFER_ABORT_STAT__out_t TRANSFER_ABORT_STAT;
2681+
I3CCSR__I3C_EC__TTI__INTERRUPT_STATUS__TX_DESC_COMPLETE__out_t TX_DESC_COMPLETE;
26712682
I3CCSR__I3C_EC__TTI__INTERRUPT_STATUS__TRANSFER_ERR_STAT__out_t TRANSFER_ERR_STAT;
26722683
} I3CCSR__I3C_EC__TTI__INTERRUPT_STATUS__out_t;
26732684

@@ -2715,6 +2726,10 @@ package I3CCSR_pkg;
27152726
logic value;
27162727
} I3CCSR__I3C_EC__TTI__INTERRUPT_ENABLE__TRANSFER_ABORT_STAT_EN__out_t;
27172728

2729+
typedef struct packed{
2730+
logic value;
2731+
} I3CCSR__I3C_EC__TTI__INTERRUPT_ENABLE__TX_DESC_COMPLETE_EN__out_t;
2732+
27182733
typedef struct packed{
27192734
logic value;
27202735
} I3CCSR__I3C_EC__TTI__INTERRUPT_ENABLE__TRANSFER_ERR_STAT_EN__out_t;
@@ -2731,6 +2746,7 @@ package I3CCSR_pkg;
27312746
I3CCSR__I3C_EC__TTI__INTERRUPT_ENABLE__IBI_THLD_STAT_EN__out_t IBI_THLD_STAT_EN;
27322747
I3CCSR__I3C_EC__TTI__INTERRUPT_ENABLE__IBI_DONE_EN__out_t IBI_DONE_EN;
27332748
I3CCSR__I3C_EC__TTI__INTERRUPT_ENABLE__TRANSFER_ABORT_STAT_EN__out_t TRANSFER_ABORT_STAT_EN;
2749+
I3CCSR__I3C_EC__TTI__INTERRUPT_ENABLE__TX_DESC_COMPLETE_EN__out_t TX_DESC_COMPLETE_EN;
27342750
I3CCSR__I3C_EC__TTI__INTERRUPT_ENABLE__TRANSFER_ERR_STAT_EN__out_t TRANSFER_ERR_STAT_EN;
27352751
} I3CCSR__I3C_EC__TTI__INTERRUPT_ENABLE__out_t;
27362752

@@ -2778,6 +2794,10 @@ package I3CCSR_pkg;
27782794
logic value;
27792795
} I3CCSR__I3C_EC__TTI__INTERRUPT_FORCE__TRANSFER_ABORT_STAT_FORCE__out_t;
27802796

2797+
typedef struct packed{
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logic value;
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} I3CCSR__I3C_EC__TTI__INTERRUPT_FORCE__TX_DESC_COMPLETE_FORCE__out_t;
2800+
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typedef struct packed{
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logic value;
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} I3CCSR__I3C_EC__TTI__INTERRUPT_FORCE__TRANSFER_ERR_STAT_FORCE__out_t;
@@ -2794,6 +2814,7 @@ package I3CCSR_pkg;
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I3CCSR__I3C_EC__TTI__INTERRUPT_FORCE__IBI_THLD_FORCE__out_t IBI_THLD_FORCE;
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I3CCSR__I3C_EC__TTI__INTERRUPT_FORCE__IBI_DONE_FORCE__out_t IBI_DONE_FORCE;
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I3CCSR__I3C_EC__TTI__INTERRUPT_FORCE__TRANSFER_ABORT_STAT_FORCE__out_t TRANSFER_ABORT_STAT_FORCE;
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I3CCSR__I3C_EC__TTI__INTERRUPT_FORCE__TX_DESC_COMPLETE_FORCE__out_t TX_DESC_COMPLETE_FORCE;
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I3CCSR__I3C_EC__TTI__INTERRUPT_FORCE__TRANSFER_ERR_STAT_FORCE__out_t TRANSFER_ERR_STAT_FORCE;
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} I3CCSR__I3C_EC__TTI__INTERRUPT_FORCE__out_t;
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