@@ -462,6 +462,11 @@ module ccc
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assign is_byte_our_virtual_static_addr = ((command_addr == virtual_target_sta_address_i) && virtual_target_sta_address_valid_i);
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assign is_byte_virtual_addr = is_byte_our_virtual_dynamic_addr | is_byte_our_virtual_static_addr;
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+ logic direct_addr_ack;
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+
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+ assign direct_addr_ack = (command_code == `I3C_DIRECT_SETDASA ) ? ((is_byte_our_static_addr && ~ target_dyn_address_valid_i) | (is_byte_our_virtual_static_addr && ~ virtual_target_dyn_address_valid_i)) :
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+ (is_byte_our_addr | is_byte_rsvd_addr | is_byte_virtual_addr);
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+
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always_ff @ (posedge clk_i or negedge rst_ni) begin : proc_addr
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if (~ rst_ni) begin
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command_addr <= '0 ;
@@ -571,12 +576,19 @@ module ccc
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end
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TxDirectAddrAck: begin
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if (bus_tx_done_i) begin
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- if (is_byte_rsvd_addr) state_d = NextCCC;
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- else if ((is_byte_our_addr || is_byte_virtual_addr) && command_rnw) state_d = TxData;
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- else if ((is_byte_our_addr || is_byte_virtual_addr) && ~ command_rnw) begin
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- if (command_code == `I3C_DIRECT_SETXTIME ) state_d = RxSubCmdByte;
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+ if (command_code == `I3C_DIRECT_SETDASA ) begin
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+ if (is_byte_our_static_addr && target_dyn_address_valid_i) state_d = WaitForBusCond;
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+ else if (is_byte_our_virtual_static_addr && virtual_target_dyn_address_valid_i) state_d = WaitForBusCond;
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else state_d = RxData;
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- end else state_d = WaitForBusCond;
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+ end
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+ else begin
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+ if (is_byte_rsvd_addr) state_d = NextCCC;
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+ else if ((is_byte_our_addr || is_byte_virtual_addr) && command_rnw) state_d = TxData;
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+ else if ((is_byte_our_addr || is_byte_virtual_addr) && ~ command_rnw) begin
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+ if (command_code == `I3C_DIRECT_SETXTIME ) state_d = RxSubCmdByte;
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+ else state_d = RxData;
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+ end else state_d = WaitForBusCond;
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+ end
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end
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end
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@@ -662,7 +674,7 @@ module ccc
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TxDirectAddrAck: begin
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ccc_tx_req_byte = '0 ;
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ccc_tx_req_bit = '1 ;
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- ccc_tx_req_value = { 7'h00 , ~ (is_byte_our_addr | is_byte_rsvd_addr | is_byte_virtual_addr) } ;
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+ ccc_tx_req_value = { 7'h00 , ~ direct_addr_ack } ;
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end
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RxSubCmdByte: begin
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end
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