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Update testplan and enable older tests
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
1 parent 9fbd49b commit 926aa4e

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13 files changed

+370
-49
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13 files changed

+370
-49
lines changed

‎requirements.txt‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ cocotb-coverage==1.2.0
1111
cocotb-test==0.2.5
1212
cocotbext-axi==0.1.24
1313
-e git+https://github.com/alexforencich/cocotbext-i2c@e5f4aa040e3c3ce2d7deced7caabfa91321d036a#egg=cocotbext_i2c
14-
git+https://github.com/antmicro/testplanner@54b6870a1b9c1518269beafe5dfd1465a9eddae6
14+
git+https://github.com/antmicro/testplanner
1515
-e ${I3C_ROOT_DIR}/third_party/cocotbext-i3c
1616
-e ${I3C_ROOT_DIR}/tools/nox_utils
1717
-e ${I3C_ROOT_DIR}/tools/cocotb_helpers

‎third_party/cocotbext-i3c‎

‎verification/cocotb/block/ctrl_descriptor_rx/test_descriptor_rx.py‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,10 @@
1010

1111
async def setup(dut):
1212
""" """
13-
dut.tti_rx_queue_full_i.value = 0
13+
dut.tti_rx_queue_wready_i.value = 1
14+
dut.rx_byte_last_i.value = 0
15+
dut.rx_byte_err_i.value = 0
16+
dut.rx_byte_valid_i.value = 0
1417
await ClockCycles(dut.clk_i, 10)
1518

1619

‎verification/cocotb/block/ctrl_descriptor_tx/test_descriptor_tx.py‎

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,13 @@
1111
async def setup(dut):
1212
""" """
1313
await ClockCycles(dut.clk_i, 10)
14+
dut.tti_tx_desc_queue_rvalid_i.value = 0
15+
dut.recovery_mode_enter_i.value = 0
16+
dut.tti_tx_queue_rvalid_i.value = 0
17+
dut.tti_tx_queue_empty_i.value = 1
18+
dut.tx_abort_i.value = 0
19+
dut.tx_start_i.value = 1
20+
dut.tx_byte_ready_i.value = 0
1421

1522

1623
@cocotb.test()
@@ -35,15 +42,17 @@ async def test_descriptor_tx(dut: SimHandleBase):
3542
dut.tti_tx_queue_rvalid_i.value = 1
3643

3744
dut.tti_tx_queue_depth_i.value = 5
38-
data = [i for i in range(6)]
45+
dut.tti_tx_queue_empty_i.value = 0
46+
data = [i for i in range(5)]
3947
data_id = 0
4048
dut.tti_tx_queue_rdata_i.value = data[data_id]
4149

4250
for _ in range(5):
4351
await cycle(dut.clk_i, dut.tx_byte_ready_i)
4452
await ClockCycles(dut.clk_i, 3)
4553
data_id += 1
46-
dut.tti_tx_queue_rdata_i.value = data[data_id]
54+
dut.tti_tx_queue_rdata_i.value = data[data_id] if data_id < len(data) else 0
55+
await ClockCycles(dut.clk_i, 3)
4756

4857
print(dut.tx_byte_o.value)
4958
print(dut.tx_byte_last_o.value)

‎verification/cocotb/noxfile.py‎

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -276,6 +276,7 @@ def i2c_target_fsm_verify(session, test_group, test_name, coverage, simulator):
276276
"test_recovery",
277277
"test_interrupts",
278278
"test_enter_exit_hdr_mode",
279+
"test_bus_stall",
279280
"test_target_reset",
280281
"test_ccc",
281282
"test_csr_access",
@@ -294,7 +295,9 @@ def i3c_ahb_verify(session, test_group, test_name, coverage, simulator):
294295
[
295296
"test_i3c_target",
296297
"test_recovery",
298+
"test_interrupts",
297299
"test_enter_exit_hdr_mode",
300+
"test_bus_stall",
298301
"test_target_reset",
299302
"test_ccc",
300303
"test_csr_access",
@@ -377,6 +380,34 @@ def ctrl_edge_detector_verify(session, test_group, test_name, coverage, simulato
377380
verify_block(session, test_group, test_name, coverage, simulator)
378381

379382

383+
@nox.session(tags=["tests", "ahb", "axi"])
384+
@nox.parametrize("test_group", ["ctrl_descriptor_tx"])
385+
@nox.parametrize(
386+
"test_name",
387+
[
388+
"test_descriptor_tx",
389+
],
390+
)
391+
@nox.parametrize("coverage", coverage_types)
392+
@nox.parametrize("simulator", simulators)
393+
def ctrl_descriptor_tx_verify(session, test_group, test_name, coverage, simulator):
394+
verify_block(session, test_group, test_name, coverage, simulator)
395+
396+
397+
@nox.session(tags=["tests", "ahb", "axi"])
398+
@nox.parametrize("test_group", ["ctrl_descriptor_rx"])
399+
@nox.parametrize(
400+
"test_name",
401+
[
402+
"test_descriptor_rx",
403+
],
404+
)
405+
@nox.parametrize("coverage", coverage_types)
406+
@nox.parametrize("simulator", simulators)
407+
def ctrl_descriptor_rx_verify(session, test_group, test_name, coverage, simulator):
408+
verify_block(session, test_group, test_name, coverage, simulator)
409+
410+
380411
@nox.session(reuse_venv=True)
381412
def lint(session: nox.Session) -> None:
382413
"""Options are defined in pyproject.toml and .flake8 files"""

‎verification/testplan/source-maps.yml‎

Lines changed: 60 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -1,24 +1,61 @@
11
testplans:
2-
- Recovery mode tests:
3-
- verification/cocotb/top/lib_i3c_top/test_recovery.py
4-
- Enter and exit HDR mode:
5-
- verification/cocotb/top/lib_i3c_top/test_enter_exit_hdr_mode.py
6-
- target_interrupts:
7-
- verification/cocotb/top/lib_i3c_top/test_interrupts.py
8-
- target_peripheral_reset:
9-
- verification/cocotb/top/lib_i3c_top/test_target_reset.py
10-
- pec:
11-
- verification/cocotb/block/recovery_pec/test_pec.py
12-
- CCC handling:
13-
- verification/cocotb/top/lib_i3c_top/test_ccc.py
14-
- width_converter_[N8]to[N8]:
15-
- verification/cocotb/block/{name}/test_converter.py
16-
- Target:
17-
- verification/cocotb/top/lib_i3c_top/test_i3c_target.py
18-
- Recovery bypass:
19-
- verification/cocotb/top/lib_i3c_top/test_bypass.py
20-
- .*:
21-
- verification/cocotb/block/ctrl_{name}/test_{name}.py
22-
- verification/cocotb/block/{name}/test_{name}.py
23-
- verification/cocotb/block/lib_adapter/test_{name}.py
24-
- verification/cocotb/block/lib_hci_queues/{name}.py
2+
- name: 'Data over-/underflow handling'
3+
testpoints:
4+
- name: "^(.*)$"
5+
source: "verification/cocotb/top/lib_i3c_top/test_bus_stall.py"
6+
- name: 'Recovery bypass'
7+
testpoints:
8+
- name: "^(.*)$"
9+
source: "verification/cocotb/top/lib_i3c_top/test_bypass.py"
10+
- name: 'CCC handling'
11+
testpoints:
12+
- name: "^(.*)$"
13+
source: "verification/cocotb/top/lib_i3c_top/test_ccc.py"
14+
- name: 'CSR access check'
15+
testpoints:
16+
- name: "^(.*)$"
17+
source: "verification/cocotb/top/lib_i3c_top/test_csr_access.py"
18+
- name: 'Enter and exit HDR mode'
19+
testpoints:
20+
- name: "^(.*)$"
21+
source: "verification/cocotb/top/lib_i3c_top/test_enter_exit_hdr_mode.py"
22+
- name: 'Target'
23+
testpoints:
24+
- name: "^(.*)$"
25+
source: "verification/cocotb/top/lib_i3c_top/test_i3c_target.py"
26+
- name: 'Target interrupts'
27+
testpoints:
28+
- name: "^(.*)$"
29+
source: "verification/cocotb/top/lib_i3c_top/test_interrupts.py"
30+
- name: 'Recovery mode tests'
31+
testpoints:
32+
- name: "^(.*)$"
33+
source: "verification/cocotb/top/lib_i3c_top/test_recovery.py"
34+
- name: 'target_peripheral_reset'
35+
testpoints:
36+
- name: "^(.*)$"
37+
source: "verification/cocotb/top/lib_i3c_top/test_target_reset.py"
38+
- name: 'pec'
39+
testpoints:
40+
- name: "^(.*)$"
41+
source: "verification/cocotb/block/recovery_pec/test_pec.py"
42+
- name: 'width_converter_[N8]to[N8]'
43+
testpoints:
44+
- name: "^(.*)$"
45+
source: "verification/cocotb/block/{{testplan}}/test_converter.py"
46+
- name: 'axi_filtering'
47+
testpoints:
48+
- name: "^(.*)$"
49+
tests:
50+
- name: "^.*(hci|pio|csr|device_addr).*$"
51+
source: "verification/cocotb/block/axi_adapter_id_filter/test_seq_csr_access.py"
52+
- name: "^.*(swap|toggle).*$"
53+
source: "verification/cocotb/block/axi_adapter_id_filter/test_runtime_id_change.py"
54+
- name: "^(.*)$"
55+
source: "verification/cocotb/block/axi_adapter_id_filter/test_bus_stress.py"
56+
- name: "^(bus_.x.*|ccc)$"
57+
source: "verification/cocotb/block/{{testplan}}/test_{{testplan}}.py"
58+
- name: "^(bus_.*)$"
59+
source: "verification/cocotb/block/ctrl_{{testplan}}/test_{{testplan}}.py"
60+
- name: "^csr_sw_access$"
61+
source: "verification/cocotb/block/lib_adapter/test_{{testplan}}.py"

‎verification/testplan/top/target.hjson‎

Lines changed: 55 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,35 @@
4242
tests: ["i3c_target_read"]
4343
tags: ["top"]
4444
}
45+
{
46+
name: i3c_target_read_empty
47+
desc:
48+
'''
49+
Issues multiple read transactions to the target and randomly selects,
50+
which if transaction has data.
51+
52+
If transaction is selected to contain data, writes a data chunk and
53+
its descriptor to TTI TX queues, and verifies that the data matches.
54+
55+
If transaction doesn't contain data, checks that request is NACKed.
56+
'''
57+
tests: ["i3c_target_read_empty"]
58+
tags: ["top"]
59+
}
60+
{
61+
name: i3c_target_read_to_multiple_targets
62+
desc:
63+
'''
64+
Sends multiple I3C frame, each containing multiple read transactions
65+
with randomly selected addresses.
66+
If transaction addresses I3C target, randomly selects if transaction
67+
returns data or is NACked. Compares returned data if available.
68+
69+
If transaction doesn't address I3C target, expects NACK to be returned.
70+
'''
71+
tests: ["i3c_target_read_to_multiple_targets"]
72+
tags: ["top"]
73+
}
4574
{
4675
name: i3c_target_ibi
4776
desc:
@@ -125,5 +154,31 @@
125154
tests: ["i3c_target_writes_and_reads"]
126155
tags: ["top"]
127156
}
157+
{
158+
name: i3c_target_pwrite_err_detection
159+
desc:
160+
'''
161+
Verifies target reports no error conditions using CSR and GETSTATUS CCC.
162+
Sends I3C private write with incorrect T-bit value.
163+
Checks that the CSR reports protocol error condition and checks
164+
that RX descriptor has error condition flag set.
165+
Sends GETSTATUS CCC and checks that it also reports protocol error.
166+
'''
167+
tests: ["i3c_target_pwrite_err_detection"]
168+
tags: ["top"]
169+
}
170+
{
171+
name: i3c_target_pwrite_overflow_detection
172+
desc:
173+
'''
174+
Verifies target reports no error conditions using CSR and GETSTATUS CCC.
175+
Sends I3C private write with more data than target can receive.
176+
Checks that the CSR doesn't report protocol error condition and checks
177+
that RX descriptor has error condition flag set.
178+
Sends GETSTATUS CCC and checks that it also doesn't report protocol error.
179+
'''
180+
tests: ["i3c_target_pwrite_overflow_detection"]
181+
tags: ["top"]
182+
}
128183
]
129184
}

‎verification/testplan/top/target_bus_stall.hjson‎

Lines changed: 66 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,66 @@
1+
{
2+
name: Data over-/underflow handling
3+
testpoints:
4+
[
5+
{
6+
name: Reading from empty RX descriptor FIFO
7+
desc:
8+
'''
9+
Perform read bus access to the empty RX descriptor queue,
10+
verify that response comes back and it holds value of 0.
11+
'''
12+
tests: ["empty_rx_desc_read"]
13+
tags: ["top"]
14+
}
15+
{
16+
name: Reading from empty RX data FIFO
17+
desc:
18+
'''
19+
Perform read bus access to the empty RX descriptor queue,
20+
verify that response comes back and it holds value of 0.
21+
'''
22+
tests: ["empty_rx_data_read"]
23+
tags: ["top"]
24+
}
25+
{
26+
name: Reading from empty indirect FIFO
27+
desc:
28+
'''
29+
Perform read bus access to the empty RX descriptor queue,
30+
verify that response comes back and it holds value of 0.
31+
'''
32+
tests: ["empty_indirect_fifo_read"]
33+
tags: ["top"]
34+
}
35+
{
36+
name: Writing to full TX descriptor FIFO
37+
desc:
38+
'''
39+
Perform multiple write bus accesses to the TX descriptor queue,
40+
verify that all transactions has finished.
41+
'''
42+
tests: ["full_tx_desc_write"]
43+
tags: ["top"]
44+
}
45+
{
46+
name: Writing to full TX data FIFO
47+
desc:
48+
'''
49+
Perform multiple write bus accesses to the TX data queue,
50+
verify that all transactions has finished.
51+
'''
52+
tests: ["full_tx_data_write"]
53+
tags: ["top"]
54+
}
55+
{
56+
name: Writing to full IBI FIFO
57+
desc:
58+
'''
59+
Perform multiple write bus accesses to the IBI queue,
60+
verify that all transactions has finished.
61+
'''
62+
tests: ["full_ibi_write"]
63+
tags: ["top"]
64+
}
65+
]
66+
}

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