i3c_config: Enable ID filtering by default

Disables ID filtering for older tests as their default behavior of
AXI TID for issuing reads & writes is to incremental with regards to the
transaction.

Signed-off-by: Wiktoria Kuna <[email protected]>

Author: wkkuna

i3c_core_configs.yaml

@@ -46,7 +46,8 @@ axi:
   FrontendBusDataWidth: 32
   FrontendBusUserWidth: 32
   FrontendBusIdWidth: 8
-  FrontendBusIdFiltering: False
+  FrontendBusIdFiltering: True
+  NumPrivIds: 4
   DisableInputFF: True
 
 axi_ff:
@@ -63,5 +64,6 @@ axi_ff:
   FrontendBusDataWidth: 32
   FrontendBusUserWidth: 32
   FrontendBusIdWidth: 8
-  FrontendBusIdFiltering: False
+  FrontendBusIdFiltering: True
+  NumPrivIds: 4
   DisableInputFF: False

src/i3c_defines.svh

@@ -17,6 +17,8 @@
   `define AXI_DATA_WIDTH   32
   `define AXI_USER_WIDTH   32
   `define AXI_ID_WIDTH     8
+  `define AXI_ID_FILTERING 1
+  `define NUM_PRIV_IDS     4
   `define DISABLE_INPUT_FF 1
 
 `endif  // I3C_CONFIG

verification/cocotb/block/axi_adapter/test_bus_stress.py

@@ -58,6 +58,9 @@ async def initialize(dut, timeout=50):
     dut.wvalid.value = 0
     dut.bready.value = 0
 
+    if hasattr(dut, "disable_id_filtering_i"):
+        dut.disable_id_filtering_i.value = 1
+
     # Configure testbench
     tb = get_frontend_bus_if()(dut)
     tb.log = dut._log

verification/cocotb/block/hci_queues_axi/hci_queues_wrapper.sv

@@ -1,4 +1,5 @@
 // SPDX-License-Identifier: Apache-2.0
+`include "i3c_defines.svh"
 
 module hci_queues_wrapper
   import i3c_pkg::*;
@@ -12,6 +13,9 @@ module hci_queues_wrapper
     parameter int unsigned AxiDataWidth = 32,
     parameter int unsigned AxiUserWidth = 32,
     parameter int unsigned AxiIdWidth   = 2,
+`ifdef AXI_ID_FILTERING
+    parameter int unsigned NumPrivIds = 4,
+`endif
 
     parameter int unsigned HciRespFifoDepth = 64,
     parameter int unsigned HciCmdFifoDepth  = 64,
@@ -107,7 +111,7 @@ module hci_queues_wrapper
 
 `ifdef AXI_ID_FILTERING
     input logic disable_id_filtering_i,
-    input logic [AxiIdWidth-1:0] priv_ids_i [NumPrivIds-1],
+    input logic [AxiIdWidth-1:0] priv_ids_i [NumPrivIds],
 `endif
 
     // HCI queues (FSM side)

verification/cocotb/block/lib_adapter/test_csr_sw_access.py

@@ -30,6 +30,14 @@
 from cocotb.handle import SimHandleBase
 
 
+# Disable AXI ID filtering to let the CSR requests pass through
+def disable_id_filtering(dut):
+    if hasattr(dut, "disable_id_filtering_i"):
+        dut.disable_id_filtering_i.value = 1
+    if hasattr(dut, "priv_ids_i"):
+        dut.priv_ids_i.value = [0] * len(dut.priv_ids_i)
+
+
 async def read_csr_and_verify(
     testIf: FrontBusTestInterface,
     addr: int,
@@ -67,7 +75,7 @@ async def write_csr_and_verify(
 @cocotb.test()
 async def test_read_hci_version_csr(dut: SimHandleBase):
     """Run test to read HCI version register."""
-
+    disable_id_filtering(dut)
     tb = get_frontend_bus_if()(dut)
     await tb.register_test_interfaces()
 
@@ -80,7 +88,7 @@ async def test_read_hci_version_csr(dut: SimHandleBase):
 @cocotb.test()
 async def test_read_pio_section_offset(dut: SimHandleBase):
     """Run test to read PIO section offset register."""
-
+    disable_id_filtering(dut)
     tb = get_frontend_bus_if()(dut)
     await tb.register_test_interfaces()
 
@@ -90,7 +98,7 @@ async def test_read_pio_section_offset(dut: SimHandleBase):
 @cocotb.test()
 async def test_write_to_controller_device_addr(dut: SimHandleBase):
     """Run test to write & read from Controller Device Address."""
-
+    disable_id_filtering(dut)
     tb = get_frontend_bus_if()(dut)
     await tb.register_test_interfaces()
 
@@ -104,7 +112,7 @@ async def test_write_to_controller_device_addr(dut: SimHandleBase):
 @cocotb.test()
 async def test_write_should_not_affect_ro_csr(dut: SimHandleBase):
     """Run test to write to RO HC Capabilities."""
-
+    disable_id_filtering(dut)
     tb = get_frontend_bus_if()(dut)
     await tb.register_test_interfaces()
 
@@ -119,6 +127,7 @@ async def test_write_should_not_affect_ro_csr(dut: SimHandleBase):
 
 @cocotb.test()
 async def test_sequence_csr_read(dut: SimHandleBase):
+    disable_id_filtering(dut)
     tb = get_frontend_bus_if()(dut)
     await tb.register_test_interfaces()
 
@@ -153,6 +162,7 @@ async def test_sequence_csr_read(dut: SimHandleBase):
 
 @cocotb.test()
 async def test_sequence_csr_write(dut: SimHandleBase):
+    disable_id_filtering(dut)
     tb = get_frontend_bus_if()(dut)
     await tb.register_test_interfaces()
 

verification/cocotb/block/lib_hci_queues/hci_queues.py

@@ -28,6 +28,9 @@ async def setup(self):
         self.dut.tti_ibi_rready_i.value = 0
         self.dut.bypass_i3c_core_i.value = 0
 
+        if hasattr(self.dut, "disable_id_filtering_i"):
+            self.dut.disable_id_filtering_i.value = 1
+
         await super()._setup(get_frontend_bus_if())
 
     async def reset(self):

verification/cocotb/top/lib_i3c_top/i3c_test_wrapper.sv

@@ -16,6 +16,9 @@ module i3c_test_wrapper #(
     parameter int unsigned AxiAddrWidth = `AXI_ADDR_WIDTH,
     parameter int unsigned AxiUserWidth = `AXI_USER_WIDTH,
     parameter int unsigned AxiIdWidth = `AXI_ID_WIDTH,
+`ifdef AXI_ID_FILTERING
+    parameter int unsigned NumPrivIds = `NUM_PRIV_IDS,
+`endif
 `endif
     parameter int unsigned DatAw = i3c_pkg::DatAw,
     parameter int unsigned DctAw = i3c_pkg::DctAw,
@@ -86,7 +89,7 @@ module i3c_test_wrapper #(
 
 `ifdef AXI_ID_FILTERING
     input logic disable_id_filtering_i,
-    input logic [AxiIdWidth-1:0] priv_ids_i [NumPrivIds-1],
+    input logic [AxiIdWidth-1:0] priv_ids_i [NumPrivIds],
 `endif
 `endif
     // I3C Target Simulation model

verification/cocotb/top/lib_i3c_top/interface.py

@@ -36,6 +36,9 @@ async def setup(self, fclk=500.0):
                 self.dut._log.warning(f"Enforcing min. system clock frequency of {fmin:.3f} MHz")
                 fclk = fmin
 
+        if hasattr(self.dut, "disable_id_filtering_i"):
+            self.dut.disable_id_filtering_i.value = 1
+
         await self.busIf.register_test_interfaces(fclk)
         await ClockCycles(self.clk, 20)
         await reset_n(self.clk, self.rst_n, cycles=5)