rdl: base: Set PRESENT_STATE 'reset' to 0

At the current implementation stage I3C is always in the standby mode.

Signed-off-by: Wiktoria Kuna <[email protected]>

Author: wkkuna

src/csr/I3CCSR_uvm.sv

@@ -310,7 +310,7 @@ package I3CCSR_uvm;
 
         virtual function void build();
             this.AC_CURRENT_OWN = new("AC_CURRENT_OWN");
-            this.AC_CURRENT_OWN.configure(this, 1, 2, "RO", 1, 'h1, 1, 1, 0);
+            this.AC_CURRENT_OWN.configure(this, 1, 2, "RO", 1, 'h0, 1, 1, 0);
             if (has_coverage(UVM_CVR_REG_BITS)) begin
                 foreach(AC_CURRENT_OWN_bit_cg[bt]) AC_CURRENT_OWN_bit_cg[bt] = new();
             end

src/rdl/base_registers.rdl

@@ -375,7 +375,7 @@ regfile BaseRegs #(
                 1 - bus owner";
             sw = r;
             hw = w;
-            reset = 1'b1;
+            reset = 1'b0;
         } AC_CURRENT_OWN[2:2];
     } PRESENT_STATE @ 0x14;
     reg {

src/rdl/docs/README.md

@@ -300,7 +300,7 @@ Don't override. Generated from: I3CCSR
 
 |Bits|  Identifier  |Access|Reset|     Name     |
 |----|--------------|------|-----|--------------|
-|  2 |AC_CURRENT_OWN|   r  | 0x1 |AC_CURRENT_OWN|
+|  2 |AC_CURRENT_OWN|   r  | 0x0 |AC_CURRENT_OWN|
 
 #### AC_CURRENT_OWN field
 

verification/cocotb/common/reg_map.py

@@ -350,7 +350,7 @@
             "AC_CURRENT_OWN": {
                 "low": 2,
                 "mask": 4,
-                "reset": 1,
+                "reset": 0,
                 "sw": "r",
                 "hw": "w",
                 "woclr": 0,