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| 1 | +axi-adapter-hci-queues-i3c-test-waivers: |
| 2 | + only: |
| 3 | + - axi_adapter_wrapper |
| 4 | + - hci_queues_wrapper |
| 5 | + - i3c_test_wrapper |
| 6 | + signals: |
| 7 | + # Following registers are currently not handled |
| 8 | + # Tied to '0 |
| 9 | + - hwif_in.I3C_EC.CtrlCfg.CONTROLLER_CONFIG.* |
| 10 | + - hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_GETCAPS.* |
| 11 | + - hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_DYNAMIC_ADDR.* |
| 12 | + - hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_TIME_PERIPHERAL.* |
| 13 | + - hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_TIME_TARGET.* |
| 14 | + - hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RST_ACTION.* |
| 15 | + - hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL.* |
| 16 | + - hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_ADDR.STATIC_ADDR.* |
| 17 | + - hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_ADDR.STATIC_ADDR_VALID.* |
| 18 | + - hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE.* |
| 19 | + - hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE.* |
| 20 | + - hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS.* |
| 21 | + - hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_STATUS.* |
| 22 | + - hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_VIRT_DEVICE_ADDR.VIRT_STATIC_ADDR.* |
| 23 | + - hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_VIRT_DEVICE_ADDR.VIRT_STATIC_ADDR_VALID.* |
| 24 | + - hwif_in.I3C_EC.TTI.INTERRUPT_STATUS.IBI_THLD_STAT.* |
| 25 | + - hwif_in.I3C_EC.TTI.INTERRUPT_STATUS.PENDING_INTERRUPT.* |
| 26 | + - hwif_in.I3C_EC.TTI.INTERRUPT_STATUS.RX_DESC_TIMEOUT.* |
| 27 | + - hwif_in.I3C_EC.TTI.INTERRUPT_STATUS.TRANSFER_ABORT_STAT.* |
| 28 | + - hwif_in.I3C_EC.TTI.INTERRUPT_STATUS.TRANSFER_ERR_STAT.* |
| 29 | + - hwif_in.I3C_EC.TTI.INTERRUPT_STATUS.TX_DATA_THLD_STAT.* |
| 30 | + - hwif_in.I3C_EC.TTI.INTERRUPT_STATUS.TX_DESC_THLD_STAT.* |
| 31 | + - hwif_in.I3C_EC.TTI.INTERRUPT_STATUS.TX_DESC_TIMEOUT.* |
| 32 | + - hwif_in.I3C_EC.TTI.QUEUE_THLD_CTRL.IBI_THLD.* |
| 33 | + - hwif_in.I3C_EC.TTI.RESET_CONTROL.SOFT_RST.* |
| 34 | + # Read-only by both SW and HW, tied to const |
| 35 | + - hwif_out.I3C_EC.CtrlCfg.EXTCAP_HEADER.* |
| 36 | + - hwif_out.I3C_EC.SoCMgmtIf.EXTCAP_HEADER.* |
| 37 | + - hwif_out.I3C_EC.StdbyCtrlMode.EXTCAP_HEADER.* |
| 38 | + - hwif_out.I3C_EC.StdbyCtrlMode.STBY_CR_CAPABILITIES.DAA_ENTDAA_SUPPORT.* |
| 39 | + - hwif_out.I3C_EC.StdbyCtrlMode.STBY_CR_CAPABILITIES.DAA_SETAASA_SUPPORT.* |
| 40 | + - hwif_out.I3C_EC.StdbyCtrlMode.STBY_CR_CAPABILITIES.DAA_SETDASA_SUPPORT.* |
| 41 | + - hwif_out.I3C_EC.StdbyCtrlMode.STBY_CR_CAPABILITIES.SIMPLE_CRR_SUPPORT.* |
| 42 | + - hwif_out.I3C_EC.StdbyCtrlMode.STBY_CR_CAPABILITIES.TARGET_XACT_SUPPORT.* |
| 43 | + - hwif_out.I3C_EC.TERMINATION_EXTCAP_HEADER.* |
| 44 | + - hwif_out.I3C_EC.TTI.QUEUE_SIZE.* |
| 45 | + # Reserved, some of them are signals in some cases and groups of signals in the other |
| 46 | + - DEVICE_ID_RESERVED |
| 47 | + - DEVICE_ID_RESERVED.* |
| 48 | + - INDIRECT_FIFO_RESERVED |
| 49 | + - INDIRECT_FIFO_RESERVED.* |
| 50 | + - RESERVED_7_3.* |
| 51 | + - SOC_MGMT_RSVD_2 |
| 52 | + - SOC_MGMT_RSVD_2.* |
| 53 | + - SOC_MGMT_RSVD_3 |
| 54 | + - SOC_MGMT_RSVD_3.* |
| 55 | + - __rsvd_3 |
| 56 | + - __rsvd_3.* |
| 57 | + |
| 58 | +i2c-and-i3c-test-waivers: |
| 59 | + only: |
| 60 | + - controller_standby_i2c_harness |
| 61 | + - flow_standby_i2c_harness |
| 62 | + - i3c_test_wrapper |
| 63 | + signals: |
| 64 | + # Reserved |
| 65 | + - __rsvd14_0 |
| 66 | + - __rsvd23_16 |
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