Clear FIFO reset after reset execution

Internal-tag: [#74403]

Author: robertszczepanski

src/csr/I3CCSR.sv

@@ -5564,12 +5564,15 @@ module I3CCSR (
         automatic logic load_next_c;
         next_c = field_storage.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_CTRL_0.RESET.value;
         load_next_c = '0;
-        if(decoded_reg_strb.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_CTRL_0 && decoded_req_is_wr) begin // SW write 1 clear
-            next_c = field_storage.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_CTRL_0.RESET.value & ~(decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
+        if(decoded_reg_strb.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_CTRL_0 && decoded_req_is_wr) begin // SW write
+            next_c = (field_storage.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_CTRL_0.RESET.value & ~decoded_wr_biten[15:8]) | (decoded_wr_data[15:8] & decoded_wr_biten[15:8]);
             load_next_c = '1;
         end else if(hwif_in.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_CTRL_0.RESET.we) begin // HW Write - we
             next_c = hwif_in.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_CTRL_0.RESET.next;
             load_next_c = '1;
+        end else if(hwif_in.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_CTRL_0.RESET.hwclr) begin // HW Clear
+            next_c = '0;
+            load_next_c = '1;
         end
         field_combo.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_CTRL_0.RESET.next = next_c;
         field_combo.I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_CTRL_0.RESET.load_next = load_next_c;

src/csr/I3CCSR_pkg.sv

@@ -497,6 +497,7 @@ package I3CCSR_pkg;
     typedef struct packed{
         logic [7:0] next;
         logic we;
+        logic hwclr;
     } I3CCSR__I3C_EC__SecFwRecoveryIf__INDIRECT_FIFO_CTRL_0__RESET__in_t;
 
     typedef struct packed{

src/csr/I3CCSR_uvm.sv

@@ -2423,7 +2423,7 @@ package I3CCSR_uvm;
             this.CMS = new("CMS");
             this.CMS.configure(this, 8, 0, "RW", 1, 'h0, 1, 1, 0);
             this.RESET = new("RESET");
-            this.RESET.configure(this, 8, 8, "W1C", 1, 'h0, 1, 1, 0);
+            this.RESET.configure(this, 8, 8, "RW", 1, 'h0, 1, 1, 0);
             if (has_coverage(UVM_CVR_REG_BITS)) begin
                 foreach(CMS_bit_cg[bt]) CMS_bit_cg[bt] = new();
                 foreach(RESET_bit_cg[bt]) RESET_bit_cg[bt] = new();

src/rdl/docs/README.md

@@ -1772,10 +1772,10 @@ When set to 0, it holds execution of enqueued commands and runs current command
 - Base Offset: 0x48
 - Size: 0x4
 
-|Bits|Identifier|  Access |Reset|                   Name                   |
-|----|----------|---------|-----|------------------------------------------|
-| 7:0|    CMS   |    rw   | 0x0 |Indirect FIFO memory access configuration.|
-|15:8|   RESET  |rw, woclr| 0x0 |   Indirect memory configuration - reset  |
+|Bits|Identifier|Access|Reset|                   Name                   |
+|----|----------|------|-----|------------------------------------------|
+| 7:0|    CMS   |  rw  | 0x0 |Indirect FIFO memory access configuration.|
+|15:8|   RESET  |  rw  | 0x0 |   Indirect memory configuration - reset  |
 
 #### CMS field
 

src/rdl/secure_firmware_recovery_interface.rdl

@@ -570,7 +570,7 @@ regfile SecureFirmwareRecoveryInterfaceRegisters{
             sw = rw;
             hw = rw;
             we = true;
-            onwrite = woclr;
+            hwclr = true;
             reset = 8'h00;
         } RESET[15:8];
     } INDIRECT_FIFO_CTRL_0;

src/recovery/recovery_executor.sv

@@ -630,6 +630,19 @@ module recovery_executor
     hwif_rec_o.INDIRECT_FIFO_CTRL_1.IMAGE_SIZE.next = tti_rx_rdata_i[31:0];
   end
 
+  logic fifo_reset_clear;
+  assign hwif_rec_o.INDIRECT_FIFO_CTRL_0.RESET.hwclr = fifo_reset_clear;
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (~rst_ni) begin
+      fifo_reset_clear <= '0;
+    end else if (hwif_rec_i.INDIRECT_FIFO_CTRL_0.RESET.value) begin
+      fifo_reset_clear <= 1'b1;
+    end else begin
+      fifo_reset_clear <= '0;
+    end
+  end
+
   // Force the value of FIFO_STATUS.FIFO_SIZE to IndirectFifoDepth.
   always_comb begin
     hwif_rec_o.INDIRECT_FIFO_STATUS_3.FIFO_SIZE.next = IndirectFifoDepth;

verification/cocotb/top/lib_i3c_top/test_recovery.py

@@ -348,7 +348,7 @@ async def test_write(dut):
     # Check
     protocol_status = (status >> 8) & 0xFF
     assert protocol_status == 0
-    assert data0 == 0xBBAA  # 2 MSBs are reserved
+    assert data0 == 0xAA  # 2 MSBs are reserved, 3rd MSB is W1C
     assert data1 == 0x44332211
 
 
@@ -833,7 +833,7 @@ async def test_virtual_read(dut):
             data, pec_ok = await recovery.command_read(VIRT_DYNAMIC_ADDR, cmd)
 
             is_nack = data == None and pec_ok == None
-            pec_ok  = bool(pec_ok)
+            pec_ok = bool(pec_ok)
 
             if is_nack:
                 dut._log.info("NACK")
@@ -962,9 +962,12 @@ async def test_payload_available(dut):
     # Initialize
     i3c_controller, i3c_target, tb, recovery = await initialize(dut, timeout=200)
 
-    fifo_size = dword2int(
-        await tb.read_csr(tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_STATUS_3.base_addr, 4)
-    ) * 4  # Multiply by 4 to get bytes from dwords
+    fifo_size = (
+        dword2int(
+            await tb.read_csr(tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_STATUS_3.base_addr, 4)
+        )
+        * 4
+    )  # Multiply by 4 to get bytes from dwords
 
     # set regular device dynamic address
     await i3c_controller.i3c_ccc_write(
@@ -1100,16 +1103,14 @@ async def test_indirect_fifo_reset_access(dut):
         VIRT_DYNAMIC_ADDR, I3cRecoveryInterface.Command.INDIRECT_FIFO_DATA, tx_data_before_reset
     )
 
-    # Clear FIFO (pointers too)
-    await recovery.command_write(
-        VIRT_DYNAMIC_ADDR, I3cRecoveryInterface.Command.INDIRECT_FIFO_CTRL, [0x00, 0x01, 0x00, 0x00]
-    )
+    # Wait until data propagates to Indirect FIFO
+    await ClockCycles(tb.clk, tx_data_length)
 
-    # Clear FIFO reset
+    # Clear FIFO (pointers too)
     await tb.write_csr_field(
         tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_CTRL_0.base_addr,
         tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_CTRL_0.RESET,
-        0xFF,
+        0x1,
     )
 
     # Write data to indirect FIFO through the recovery interface
@@ -1227,13 +1228,6 @@ async def bfm_agent():
 
         assert (wrptr, rdptr) == (0, 0)
 
-        # Clear FIFO reset
-        await tb.write_csr_field(
-            tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_CTRL_0.base_addr,
-            tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_CTRL_0.RESET,
-            0xFF,
-        )
-
         # Send firmware chunks
         xfer_size = 4
         for data_ptr in range(0, image_size, xfer_size * 4):