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kgugalakgugala
committed
Update CSR tests
1 parent 879a44d commit a6e939d

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10 files changed

+246
-131
lines changed

10 files changed

+246
-131
lines changed

‎src/csr/I3CCSR.sv‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -5196,8 +5196,8 @@ module I3CCSR (
51965196
if(decoded_reg_strb.I3C_EC.TTI.RESET_CONTROL && decoded_req_is_wr) begin // SW write
51975197
next_c = (field_storage.I3C_EC.TTI.RESET_CONTROL.SOFT_RST.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
51985198
load_next_c = '1;
5199-
end else if(hwif_in.I3C_EC.TTI.RESET_CONTROL.SOFT_RST.we) begin // HW Write - we
5200-
next_c = hwif_in.I3C_EC.TTI.RESET_CONTROL.SOFT_RST.next;
5199+
end else if(hwif_in.I3C_EC.TTI.RESET_CONTROL.SOFT_RST.hwclr) begin // HW Clear
5200+
next_c = '0;
52015201
load_next_c = '1;
52025202
end
52035203
field_combo.I3C_EC.TTI.RESET_CONTROL.SOFT_RST.next = next_c;
@@ -5222,8 +5222,8 @@ module I3CCSR (
52225222
if(decoded_reg_strb.I3C_EC.TTI.RESET_CONTROL && decoded_req_is_wr) begin // SW write
52235223
next_c = (field_storage.I3C_EC.TTI.RESET_CONTROL.TX_DESC_RST.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]);
52245224
load_next_c = '1;
5225-
end else if(hwif_in.I3C_EC.TTI.RESET_CONTROL.TX_DESC_RST.we) begin // HW Write - we
5226-
next_c = hwif_in.I3C_EC.TTI.RESET_CONTROL.TX_DESC_RST.next;
5225+
end else if(hwif_in.I3C_EC.TTI.RESET_CONTROL.TX_DESC_RST.hwclr) begin // HW Clear
5226+
next_c = '0;
52275227
load_next_c = '1;
52285228
end
52295229
field_combo.I3C_EC.TTI.RESET_CONTROL.TX_DESC_RST.next = next_c;
@@ -5248,8 +5248,8 @@ module I3CCSR (
52485248
if(decoded_reg_strb.I3C_EC.TTI.RESET_CONTROL && decoded_req_is_wr) begin // SW write
52495249
next_c = (field_storage.I3C_EC.TTI.RESET_CONTROL.RX_DESC_RST.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]);
52505250
load_next_c = '1;
5251-
end else if(hwif_in.I3C_EC.TTI.RESET_CONTROL.RX_DESC_RST.we) begin // HW Write - we
5252-
next_c = hwif_in.I3C_EC.TTI.RESET_CONTROL.RX_DESC_RST.next;
5251+
end else if(hwif_in.I3C_EC.TTI.RESET_CONTROL.RX_DESC_RST.hwclr) begin // HW Clear
5252+
next_c = '0;
52535253
load_next_c = '1;
52545254
end
52555255
field_combo.I3C_EC.TTI.RESET_CONTROL.RX_DESC_RST.next = next_c;
@@ -5274,8 +5274,8 @@ module I3CCSR (
52745274
if(decoded_reg_strb.I3C_EC.TTI.RESET_CONTROL && decoded_req_is_wr) begin // SW write
52755275
next_c = (field_storage.I3C_EC.TTI.RESET_CONTROL.TX_DATA_RST.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]);
52765276
load_next_c = '1;
5277-
end else if(hwif_in.I3C_EC.TTI.RESET_CONTROL.TX_DATA_RST.we) begin // HW Write - we
5278-
next_c = hwif_in.I3C_EC.TTI.RESET_CONTROL.TX_DATA_RST.next;
5277+
end else if(hwif_in.I3C_EC.TTI.RESET_CONTROL.TX_DATA_RST.hwclr) begin // HW Clear
5278+
next_c = '0;
52795279
load_next_c = '1;
52805280
end
52815281
field_combo.I3C_EC.TTI.RESET_CONTROL.TX_DATA_RST.next = next_c;
@@ -5300,8 +5300,8 @@ module I3CCSR (
53005300
if(decoded_reg_strb.I3C_EC.TTI.RESET_CONTROL && decoded_req_is_wr) begin // SW write
53015301
next_c = (field_storage.I3C_EC.TTI.RESET_CONTROL.RX_DATA_RST.value & ~decoded_wr_biten[4:4]) | (decoded_wr_data[4:4] & decoded_wr_biten[4:4]);
53025302
load_next_c = '1;
5303-
end else if(hwif_in.I3C_EC.TTI.RESET_CONTROL.RX_DATA_RST.we) begin // HW Write - we
5304-
next_c = hwif_in.I3C_EC.TTI.RESET_CONTROL.RX_DATA_RST.next;
5303+
end else if(hwif_in.I3C_EC.TTI.RESET_CONTROL.RX_DATA_RST.hwclr) begin // HW Clear
5304+
next_c = '0;
53055305
load_next_c = '1;
53065306
end
53075307
field_combo.I3C_EC.TTI.RESET_CONTROL.RX_DATA_RST.next = next_c;
@@ -5326,8 +5326,8 @@ module I3CCSR (
53265326
if(decoded_reg_strb.I3C_EC.TTI.RESET_CONTROL && decoded_req_is_wr) begin // SW write
53275327
next_c = (field_storage.I3C_EC.TTI.RESET_CONTROL.IBI_QUEUE_RST.value & ~decoded_wr_biten[5:5]) | (decoded_wr_data[5:5] & decoded_wr_biten[5:5]);
53285328
load_next_c = '1;
5329-
end else if(hwif_in.I3C_EC.TTI.RESET_CONTROL.IBI_QUEUE_RST.we) begin // HW Write - we
5330-
next_c = hwif_in.I3C_EC.TTI.RESET_CONTROL.IBI_QUEUE_RST.next;
5329+
end else if(hwif_in.I3C_EC.TTI.RESET_CONTROL.IBI_QUEUE_RST.hwclr) begin // HW Clear
5330+
next_c = '0;
53315331
load_next_c = '1;
53325332
end
53335333
field_combo.I3C_EC.TTI.RESET_CONTROL.IBI_QUEUE_RST.next = next_c;

‎src/csr/I3CCSR_pkg.sv‎

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -782,33 +782,27 @@ package I3CCSR_pkg;
782782
} I3CCSR__I3C_EC__TTI__STATUS__in_t;
783783

784784
typedef struct packed{
785-
logic next;
786-
logic we;
785+
logic hwclr;
787786
} I3CCSR__I3C_EC__TTI__RESET_CONTROL__SOFT_RST__in_t;
788787

789788
typedef struct packed{
790-
logic next;
791-
logic we;
789+
logic hwclr;
792790
} I3CCSR__I3C_EC__TTI__RESET_CONTROL__TX_DESC_RST__in_t;
793791

794792
typedef struct packed{
795-
logic next;
796-
logic we;
793+
logic hwclr;
797794
} I3CCSR__I3C_EC__TTI__RESET_CONTROL__RX_DESC_RST__in_t;
798795

799796
typedef struct packed{
800-
logic next;
801-
logic we;
797+
logic hwclr;
802798
} I3CCSR__I3C_EC__TTI__RESET_CONTROL__TX_DATA_RST__in_t;
803799

804800
typedef struct packed{
805-
logic next;
806-
logic we;
801+
logic hwclr;
807802
} I3CCSR__I3C_EC__TTI__RESET_CONTROL__RX_DATA_RST__in_t;
808803

809804
typedef struct packed{
810-
logic next;
811-
logic we;
805+
logic hwclr;
812806
} I3CCSR__I3C_EC__TTI__RESET_CONTROL__IBI_QUEUE_RST__in_t;
813807

814808
typedef struct packed{

‎src/hci/hci.sv‎

Lines changed: 6 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -205,17 +205,10 @@ module hci
205205
txrst = hwif_base_i.RESET_CONTROL.TX_FIFO_RST.value;
206206
resprst = hwif_base_i.RESET_CONTROL.RESP_QUEUE_RST.value;
207207

208-
hwif_base_o.RESET_CONTROL.CMD_QUEUE_RST.we = cmd_reset_ctrl_we;
209-
hwif_base_o.RESET_CONTROL.CMD_QUEUE_RST.next = cmd_reset_ctrl_next;
210-
211-
hwif_base_o.RESET_CONTROL.RX_FIFO_RST.we = rx_reset_ctrl_we;
212-
hwif_base_o.RESET_CONTROL.RX_FIFO_RST.next = rx_reset_ctrl_next;
213-
214-
hwif_base_o.RESET_CONTROL.TX_FIFO_RST.we = tx_reset_ctrl_we;
215-
hwif_base_o.RESET_CONTROL.TX_FIFO_RST.next = tx_reset_ctrl_next;
216-
217-
hwif_base_o.RESET_CONTROL.RESP_QUEUE_RST.we = resp_reset_ctrl_we;
218-
hwif_base_o.RESET_CONTROL.RESP_QUEUE_RST.next = resp_reset_ctrl_next;
208+
hwif_base_o.RESET_CONTROL.CMD_QUEUE_RST.hwclr = cmd_reset_ctrl_we & !cmd_reset_ctrl_next;
209+
hwif_base_o.RESET_CONTROL.RX_FIFO_RST.hwclr = rx_reset_ctrl_we & !rx_reset_ctrl_next;
210+
hwif_base_o.RESET_CONTROL.TX_FIFO_RST.hwclr = tx_reset_ctrl_we & !tx_reset_ctrl_next;
211+
hwif_base_o.RESET_CONTROL.RESP_QUEUE_RST.hwclr = resp_reset_ctrl_we & !resp_reset_ctrl_next;
219212

220213
// Threshold
221214
hwif_pio_control_o.QUEUE_THLD_CTRL.CMD_EMPTY_BUF_THLD.we = cmd_ready_thld_we;
@@ -393,9 +386,8 @@ module hci
393386
logic [HciIbiDataWidth-1:0] hci_ibi_rd_data;
394387

395388
always_comb begin
396-
hci_ibi_rst = hwif_base_i.RESET_CONTROL.IBI_QUEUE_RST.value;
397-
hwif_base_o.RESET_CONTROL.IBI_QUEUE_RST.we = hci_ibi_rst_we;
398-
hwif_base_o.RESET_CONTROL.IBI_QUEUE_RST.next = hci_ibi_rst_next;
389+
hci_ibi_rst = hwif_out_o.I3CBase.RESET_CONTROL.IBI_QUEUE_RST.value;
390+
hwif_base_o.RESET_CONTROL.IBI_QUEUE_RST.hwclr = hci_ibi_rst_we & !hci_ibi_rst_next;
399391

400392
hci_ibi_thld = hwif_pio_control_i.QUEUE_THLD_CTRL.IBI_STATUS_THLD.value;
401393

‎src/hci/tti.sv‎

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -158,8 +158,7 @@ module tti
158158
always_comb begin : wire_hwif_xfer
159159

160160
// RX_DESC_QUEUE_PORT
161-
hwif_tti_o.RESET_CONTROL.RX_DESC_RST.we = rx_desc_queue_reg_rst_we_i;
162-
hwif_tti_o.RESET_CONTROL.RX_DESC_RST.next = rx_desc_queue_reg_rst_data_i;
161+
hwif_tti_o.RESET_CONTROL.RX_DESC_RST.hwclr = rx_desc_queue_reg_rst_we_i & !rx_desc_queue_reg_rst_data_i;
163162
if (rx_desc_queue_empty_i && hwif_tti_i.RX_DESC_QUEUE_PORT.req) begin
164163
hwif_tti_o.RX_DESC_QUEUE_PORT.rd_ack = hwif_tti_i.RX_DESC_QUEUE_PORT.req & ~hwif_tti_i.RX_DESC_QUEUE_PORT.req_is_wr;
165164
hwif_tti_o.RX_DESC_QUEUE_PORT.rd_data = '0;
@@ -171,8 +170,7 @@ module tti
171170
end
172171

173172
// TX_DESC_QUEUE_PORT
174-
hwif_tti_o.RESET_CONTROL.TX_DESC_RST.we = tx_desc_queue_reg_rst_we_i;
175-
hwif_tti_o.RESET_CONTROL.TX_DESC_RST.next = tx_desc_queue_reg_rst_data_i;
173+
hwif_tti_o.RESET_CONTROL.TX_DESC_RST.hwclr = tx_desc_queue_reg_rst_we_i & !tx_desc_queue_reg_rst_data_i;
176174
if (tx_desc_queue_full_i && hwif_tti_i.TX_DESC_QUEUE_PORT.req) begin
177175
hwif_tti_o.TX_DESC_QUEUE_PORT.wr_ack = hwif_tti_i.TX_DESC_QUEUE_PORT.req & hwif_tti_i.TX_DESC_QUEUE_PORT.req_is_wr;
178176
tx_desc_queue_req_o = '0;
@@ -184,8 +182,7 @@ module tti
184182
end
185183

186184
// RX_DATA_PORT
187-
hwif_tti_o.RESET_CONTROL.RX_DATA_RST.we = rx_data_queue_reg_rst_we_i;
188-
hwif_tti_o.RESET_CONTROL.RX_DATA_RST.next = rx_data_queue_reg_rst_data_i;
185+
hwif_tti_o.RESET_CONTROL.RX_DATA_RST.hwclr = rx_data_queue_reg_rst_we_i & !rx_data_queue_reg_rst_data_i;
189186
if (rx_data_queue_empty_i && hwif_tti_i.RX_DATA_PORT.req) begin
190187
hwif_tti_o.RX_DATA_PORT.rd_ack = hwif_tti_i.RX_DATA_PORT.req & ~hwif_tti_i.RX_DATA_PORT.req_is_wr;;
191188
hwif_tti_o.RX_DATA_PORT.rd_data = '0;
@@ -197,8 +194,7 @@ module tti
197194
end
198195

199196
// TX_DATA_PORT
200-
hwif_tti_o.RESET_CONTROL.TX_DATA_RST.we = tx_data_queue_reg_rst_we_i;
201-
hwif_tti_o.RESET_CONTROL.TX_DATA_RST.next = tx_data_queue_reg_rst_data_i;
197+
hwif_tti_o.RESET_CONTROL.TX_DATA_RST.hwclr = tx_data_queue_reg_rst_we_i & !tx_data_queue_reg_rst_data_i;
202198
if (tx_data_queue_full_i && hwif_tti_i.TX_DATA_PORT.req) begin
203199
tx_data_queue_req_o = '0;
204200
tx_data_queue_data_o = '0;
@@ -210,8 +206,7 @@ module tti
210206
end
211207

212208
// IBI_PORT
213-
hwif_tti_o.RESET_CONTROL.IBI_QUEUE_RST.we = ibi_queue_reg_rst_we_i;
214-
hwif_tti_o.RESET_CONTROL.IBI_QUEUE_RST.next = ibi_queue_reg_rst_data_i;
209+
hwif_tti_o.RESET_CONTROL.IBI_QUEUE_RST.hwclr = ibi_queue_reg_rst_we_i & !ibi_queue_reg_rst_data_i;
215210
if (ibi_queue_full_i && hwif_tti_i.IBI_PORT.req) begin
216211
ibi_queue_req_o = '0;
217212
ibi_queue_data_o = '0;
@@ -247,8 +242,7 @@ module tti
247242

248243
always_comb begin : wire_unconnected_regs
249244

250-
hwif_tti_o.RESET_CONTROL.SOFT_RST.we = '0;
251-
hwif_tti_o.RESET_CONTROL.SOFT_RST.next = '0;
245+
hwif_tti_o.RESET_CONTROL.SOFT_RST.hwclr = '0;
252246

253247
hwif_tti_o.INTERRUPT_STATUS.PENDING_INTERRUPT.we = '0;
254248
hwif_tti_o.INTERRUPT_STATUS.PENDING_INTERRUPT.next = '0;

‎src/rdl/base_registers.rdl‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -319,48 +319,48 @@ regfile BaseRegs #(
319319
name = "IBI_QUEUE_RST";
320320
desc = "Clear IBI queue from software. Valid only in PIO mode.";
321321
sw = rw;
322-
hw = rw;
323-
we = true;
322+
hw = r;
323+
hwclr;
324324
reset = 1'b0;
325325
} IBI_QUEUE_RST[5:5];
326326
field {
327327
name = "RX_FIFO_RST";
328328
desc = "Clear RX FIFO from software. Valid only in PIO mode.";
329329
sw = rw;
330-
hw = rw;
331-
we = true;
330+
hw = r;
331+
hwclr;
332332
reset = 1'b0;
333333
} RX_FIFO_RST[4:4];
334334
field {
335335
name = "TX_FIFO_RST";
336336
desc = "Clear TX FIFO from software. Valid only in PIO mode.";
337337
sw = rw;
338-
hw = rw;
339-
we = true;
338+
hw = r;
339+
hwclr;
340340
reset = 1'b0;
341341
} TX_FIFO_RST[3:3];
342342
field {
343343
name = "RESP_QUEUE_RST";
344344
desc = "Clear response queue from software. Valid only in PIO mode.";
345345
sw = rw;
346-
hw = rw;
347-
we = true;
346+
hw = r;
347+
hwclr;
348348
reset = 1'b0;
349349
} RESP_QUEUE_RST[2:2];
350350
field {
351351
name = "CMD_QUEUE_RST";
352352
desc = "Clear command queue from software. Valid only in PIO mode.";
353353
sw = rw;
354-
hw = rw;
355-
we = true;
354+
hw = r;
355+
hwclr;
356356
reset = 1'b0;
357357
} CMD_QUEUE_RST[1:1];
358358
field {
359359
name = "SOFT_RST";
360360
desc = "Reset controller from software.";
361361
sw = rw;
362-
hw = rw;
363-
we = true;
362+
hw = r;
363+
hwclr;
364364
reset = 1'b0;
365365
} SOFT_RST[0:0];
366366
} RESET_CONTROL @ 0x10;

‎src/rdl/target_transaction_interface.rdl‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -139,48 +139,48 @@ regfile TargetTransactionInterfaceRegisters #(
139139
name = "IBI_QUEUE_RST";
140140
desc = "TTI IBI Queue Buffer Software Reset";
141141
sw = rw;
142-
hw = rw;
143-
we = true;
142+
hw = r;
143+
hwclr;
144144
reset = 1'b0;
145145
} IBI_QUEUE_RST[5:5];
146146
field {
147147
name = "RX_DATA_RST";
148148
desc = "TTI RX Data Queue Buffer Software Reset";
149149
sw = rw;
150-
hw = rw;
151-
we = true;
150+
hw = r;
151+
hwclr;
152152
reset = 1'b0;
153153
} RX_DATA_RST[4:4];
154154
field {
155155
name = "TX_DATA_RST";
156156
desc = "TTI TX Data Queue Buffer Software Reset";
157157
sw = rw;
158-
hw = rw;
159-
we = true;
158+
hw = r;
159+
hwclr;
160160
reset = 1'b0;
161161
} TX_DATA_RST[3:3];
162162
field {
163163
name = "RX_DESC_RST";
164164
desc = "TTI RX Descriptor Queue Buffer Software Reset";
165165
sw = rw;
166-
hw = rw;
167-
we = true;
166+
hw = r;
167+
hwclr;
168168
reset = 1'b0;
169169
} RX_DESC_RST[2:2];
170170
field {
171171
name = "TX_DESC_RST";
172172
desc = "TTI TX Descriptor Queue Buffer Software Reset";
173173
sw = rw;
174-
hw = rw;
175-
we = true;
174+
hw = r;
175+
hwclr;
176176
reset = 1'b0;
177177
} TX_DESC_RST[1:1];
178178
field {
179179
name = "SOFT_RST";
180180
desc = "Target Core Software Reset";
181181
sw = rw;
182-
hw = rw;
183-
we = true;
182+
hw = r;
183+
hwclr;
184184
reset = 1'b0;
185185
} SOFT_RST[0:0];
186186
} RESET_CONTROL;

‎verification/cocotb/block/ahb_if/ahb_if_wrapper.sv‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -109,12 +109,12 @@ module ahb_if_wrapper
109109
hwif_in.I3CBase.HC_CONTROL.BUS_ENABLE.we = 0;
110110
hwif_in.I3CBase.CONTROLLER_DEVICE_ADDR.DYNAMIC_ADDR.we = 0;
111111
hwif_in.I3CBase.CONTROLLER_DEVICE_ADDR.DYNAMIC_ADDR_VALID.we = 0;
112-
hwif_in.I3CBase.RESET_CONTROL.SOFT_RST.we = 0;
113-
hwif_in.I3CBase.RESET_CONTROL.CMD_QUEUE_RST.we = 0;
114-
hwif_in.I3CBase.RESET_CONTROL.RESP_QUEUE_RST.we = 0;
115-
hwif_in.I3CBase.RESET_CONTROL.TX_FIFO_RST.we = 0;
116-
hwif_in.I3CBase.RESET_CONTROL.RX_FIFO_RST.we = 0;
117-
hwif_in.I3CBase.RESET_CONTROL.IBI_QUEUE_RST.we = 0;
112+
hwif_in.I3CBase.RESET_CONTROL.SOFT_RST.hwclr = '0;
113+
hwif_in.I3CBase.RESET_CONTROL.CMD_QUEUE_RST.hwclr = '0;
114+
hwif_in.I3CBase.RESET_CONTROL.RESP_QUEUE_RST.hwclr = '0;
115+
hwif_in.I3CBase.RESET_CONTROL.TX_FIFO_RST.hwclr = '0;
116+
hwif_in.I3CBase.RESET_CONTROL.RX_FIFO_RST.hwclr = '0;
117+
hwif_in.I3CBase.RESET_CONTROL.IBI_QUEUE_RST.hwclr = '0;
118118
hwif_in.I3CBase.DCT_SECTION_OFFSET.TABLE_INDEX.we = 0;
119119
hwif_in.I3CBase.IBI_DATA_ABORT_CTRL.IBI_DATA_ABORT_MON.we = 0;
120120
hwif_in.PIOControl.QUEUE_THLD_CTRL.CMD_EMPTY_BUF_THLD.we = 0;
@@ -126,12 +126,12 @@ module ahb_if_wrapper
126126
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL.DAA_SETDASA_ENABLE.we = 0;
127127
hwif_in.I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL.DAA_ENTDAA_ENABLE.we = 0;
128128
`ifdef TARGET_SUPPORT
129-
hwif_in.I3C_EC.TTI.RESET_CONTROL.SOFT_RST.we = 0;
130-
hwif_in.I3C_EC.TTI.RESET_CONTROL.TX_DESC_RST.we = 0;
131-
hwif_in.I3C_EC.TTI.RESET_CONTROL.RX_DESC_RST.we = 0;
132-
hwif_in.I3C_EC.TTI.RESET_CONTROL.TX_DATA_RST.we = 0;
133-
hwif_in.I3C_EC.TTI.RESET_CONTROL.RX_DATA_RST.we = 0;
134-
hwif_in.I3C_EC.TTI.RESET_CONTROL.IBI_QUEUE_RST.we = 0;
129+
hwif_in.I3C_EC.TTI.RESET_CONTROL.SOFT_RST.hwclr = 0;
130+
hwif_in.I3C_EC.TTI.RESET_CONTROL.TX_DESC_RST.hwclr = 0;
131+
hwif_in.I3C_EC.TTI.RESET_CONTROL.RX_DESC_RST.hwclr = 0;
132+
hwif_in.I3C_EC.TTI.RESET_CONTROL.TX_DATA_RST.hwclr = 0;
133+
hwif_in.I3C_EC.TTI.RESET_CONTROL.RX_DATA_RST.hwclr = 0;
134+
hwif_in.I3C_EC.TTI.RESET_CONTROL.IBI_QUEUE_RST.hwclr = 0;
135135
hwif_in.I3C_EC.TTI.QUEUE_THLD_CTRL.TX_DESC_THLD.we = 0;
136136
hwif_in.I3C_EC.TTI.QUEUE_THLD_CTRL.RX_DESC_THLD.we = 0;
137137
hwif_in.I3C_EC.TTI.QUEUE_THLD_CTRL.IBI_THLD.we = 0;

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