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1 parent 40919e6 commit b360711Copy full SHA for b360711
testbench/Makefile
@@ -3,7 +3,7 @@
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VCS = vcs
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BUILD_DIR = $(I3C_ROOT_DIR)/testbench/build
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-BUILD_ARGS += +define+DIGITAL_IO_I3C -full64 -sverilog
+BUILD_ARGS += +define+DIGITAL_IO_I3C -full64 -sverilog +lint=TFIPC-L
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BUILD_ARGS += +libext+.sv +libext+.v
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BUILD_ARGS += $(foreach dir,$(VERILOG_INCLUDE_DIRS),-y $(dir))
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BUILD_ARGS += -debug_access+all +memcbk -timescale=1ns/1ps
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