tests: Reduce / remove excessive waits

Signed-off-by: Wiktoria Kuna <[email protected]>

Author: wkkuna

verification/cocotb/block/axi_adapter/test_bus_stress.py

@@ -59,7 +59,6 @@ async def initialize(dut, timeout=50):
     tb = get_frontend_bus_if()(dut)
     tb.log = dut._log
     await tb.register_test_interfaces()
-    await ClockCycles(tb.clk, 20)
     await reset_n(tb.clk, tb.rst_n, cycles=5)
 
     # Generate test data

verification/cocotb/block/bus_tx/test_bus_tx.py

@@ -57,12 +57,8 @@ async def setup_test(dut, timings=None, scl_clk_ratio=SCL_CLK_RATIO):
     dut.scl_stable_low_i.value = 0
     dut.sel_od_pp_i.value = 0
 
-    await ClockCycles(dut.clk_i, 10)
-
     await reset(dut)
 
-    await ClockCycles(dut.clk_i, 10)
-
     assert dut.tx_idle_o.value == 1
     assert dut.tx_done_o.value == 0
     assert dut.sda_o.value == 1
@@ -158,7 +154,6 @@ async def test_bit_tx_negedge(dut, value, timings, ratio):
     dut.drive_value_i.value = value
 
     await assert_drive_start(dut, value)
-    await ClockCycles(dut.clk_i, 10)
 
 
 tf = TestFactory(test_function=test_bit_tx_negedge)
@@ -177,7 +172,6 @@ async def test_bit_tx_pre_posedge(dut, value):
     dut.drive_value_i.value = value
 
     await assert_drive_start(dut, value)
-    await ClockCycles(dut.clk_i, 10)
 
 
 tf = TestFactory(test_function=test_bit_tx_pre_posedge)
@@ -194,7 +188,6 @@ async def test_bit_tx_high_level(dut, value):
     dut.drive_value_i.value = value
 
     await assert_drive_start(dut, value)
-    await ClockCycles(dut.clk_i, 10)
 
 
 tf = TestFactory(test_function=test_bit_tx_high_level)
@@ -211,7 +204,6 @@ async def test_bit_tx_low_level(dut, value):
     dut.drive_value_i.value = value
 
     await assert_drive_start(dut, value)
-    await ClockCycles(dut.clk_i, 10)
 
 
 tf = TestFactory(test_function=test_bit_tx_low_level)
@@ -241,4 +233,3 @@ async def test_byte_tx(dut):
 
     # Ensure that the bus is free
     assert dut.sda_o.value == 1
-    await ClockCycles(dut.clk_i, 10)

verification/cocotb/block/bus_tx_flow/test_bus_tx_flow.py

@@ -52,9 +52,7 @@ async def setup_test(dut):
     dut.scl_stable_low_i.value = 0
     dut.sel_od_pp_i.value = 0
 
-    await ClockCycles(dut.clk_i, 10)
     await reset(dut)
-    await ClockCycles(dut.clk_i, 10)
 
     assert dut.bus_tx_idle_o.value == 1
     assert dut.bus_tx_done_o.value == 0
@@ -99,7 +97,6 @@ async def test_bit_tx_negedge(dut, value):
     dut.req_value_i.value = value
 
     await assert_bit_request(dut, value)
-    await ClockCycles(dut.clk_i, 10)
 
 
 tf = TestFactory(test_function=test_bit_tx_negedge)
@@ -116,7 +113,6 @@ async def test_bit_tx_pre_posedge(dut, value):
     dut.req_value_i.value = value
 
     await assert_bit_request(dut, value)
-    await ClockCycles(dut.clk_i, 10)
 
 
 tf = TestFactory(test_function=test_bit_tx_pre_posedge)
@@ -133,7 +129,6 @@ async def test_bit_tx_high_level(dut, value):
     dut.req_value_i.value = value
 
     await assert_bit_request(dut, value)
-    await ClockCycles(dut.clk_i, 10)
 
 
 tf = TestFactory(test_function=test_bit_tx_high_level)
@@ -150,7 +145,6 @@ async def test_bit_tx_low_level(dut, value):
     dut.req_value_i.value = value
 
     await assert_bit_request(dut, value)
-    await ClockCycles(dut.clk_i, 10)
 
 
 tf = TestFactory(test_function=test_bit_tx_low_level)
@@ -199,5 +193,3 @@ async def test_byte_tx(dut):
         await ReadOnly()
         # Ensure that the bus is free
         assert dut.sda_o.value == 1
-
-    await ClockCycles(dut.clk_i, 100)

verification/cocotb/block/ccc/test_ccc.py

@@ -126,8 +126,6 @@ async def get_status(dut):
 
     # Stop the frame
     await cycle(dut.clk_i, dut.bus_stop_det_i)
-    await ClockCycles(dut.clk_i, 5)
-
     return status
 
 

verification/cocotb/block/ctrl_bus_monitor/test_bus_monitor.py

@@ -19,7 +19,6 @@ async def setup(dut):
     dut.t_hd_dat_i.value = 0x05
     dut.t_r_i.value = 0x02
     dut.t_f_i.value = 0x02
-    await ClockCycles(dut.clk_i, 10)
 
 
 async def count_high_cycles(clk, sig, e_terminate):
@@ -100,5 +99,3 @@ async def test_bus_monitor(dut: SimHandleBase):
         assert num_stops == 1
 
         e_terminate.clear()
-
-    await ClockCycles(clk, 10)

verification/cocotb/block/ctrl_bus_timers/test_bus_timers.py

@@ -19,7 +19,6 @@ async def setup(dut):
     dut.t_bus_available_i.value = 10
     dut.t_bus_idle_i.value = 50
     dut.restart_counter_i.value = 0
-    await ClockCycles(dut.clk_i, 10)
 
 
 @cocotb.test()

verification/cocotb/block/ctrl_i3c_bus_monitor/test_i3c_bus_monitor.py

@@ -20,7 +20,6 @@ async def setup(dut):
     dut.t_r_i.value = 0x02
     dut.t_f_i.value = 0x02
     dut.is_in_hdr_mode_i.value = 0
-    await ClockCycles(dut.clk_i, 10)
 
 
 async def count_high_cycles(clk, sig, e_terminate):
@@ -114,7 +113,7 @@ async def test_target_reset_detection(dut: SimHandleBase):
     )
     await i3c_controller.target_reset()
 
-    await ClockCycles(dut.clk_i, 32)
+    await ClockCycles(dut.clk_i, 10)
     e_terminate.set()
     await RisingEdge(dut.clk_i)
 
@@ -123,5 +122,3 @@ async def test_target_reset_detection(dut: SimHandleBase):
     assert num_resets == 1
 
     e_terminate.clear()
-
-    await ClockCycles(dut.clk_i, 10)

verification/cocotb/block/flow_standby_i3c/test_flow_standby_i3c.py

@@ -139,5 +139,3 @@ async def test_rx(dut: SimHandleBase):
     cocotb.start_soon(tx_queue.bfm(dut))
 
     await bus_tx(dut)
-
-    await ClockCycles(clk, 50)

verification/cocotb/block/i2c_controller_fsm/test_mem_rw.py

@@ -38,13 +38,12 @@ async def test_mem_rw(dut):
 
     # Execute single I2C command test -----------------------------------------
     await i2c_cmd(dut, I2C_REG_ADDR << 1, sta_before=True, sto_after=True)
-    await ClockCycles(dut.clk_i, 100)
 
     # Execute single read & write test ----------------------------------------
     # Write single byte to I2C memory
     TEST_PAYLOAD = [random.randint(0, 255)]
     await i2c_mem_write(dut, I2C_DEV_ADDR, I2C_REG_ADDR, TEST_PAYLOAD)
-    await ClockCycles(dut.clk_i, 100)
+    await ClockCycles(dut.clk_i, 10)
 
     # Read the byte I2C memory
     received = await i2c_mem_read(dut, I2C_DEV_ADDR, I2C_REG_ADDR, 1)
@@ -57,11 +56,8 @@ async def test_mem_rw(dut):
     # Write test payload to I2C memory
     TEST_PAYLOAD = [random.randint(0, 255) for _ in range(20)]
     await i2c_mem_write(dut, I2C_DEV_ADDR, I2C_REG_ADDR, TEST_PAYLOAD)
-    await ClockCycles(dut.clk_i, 100)
+    await ClockCycles(dut.clk_i, 10)
 
     # Read payload from I2C memory
     received = await i2c_mem_read(dut, I2C_DEV_ADDR, I2C_REG_ADDR, len(TEST_PAYLOAD))
     assert received == TEST_PAYLOAD
-
-    # Dummy
-    await ClockCycles(dut.clk_i, 100)

verification/cocotb/block/i2c_standby_controller/test_read.py

@@ -16,7 +16,7 @@
 
 async def reset(dut):
     dut.rst_ni.value = 0
-    await ClockCycles(dut.clk_i, 100)
+    await ClockCycles(dut.clk_i, 2)
     await FallingEdge(dut.clk_i)
     dut.rst_ni.value = 1
     await ClockCycles(dut.clk_i, 2)