entdaa: use csrs for id

Author: kgugala

src/ctrl/ccc.sv

@@ -89,7 +89,6 @@ module ccc
 (
     input logic clk_i,  // Clock
     input logic rst_ni, // Async reset, active low
-    input logic [47:0] id_i,
 
     // CC is decoded from the frame by the primary FSM
     input logic [7:0] ccc_i,
@@ -240,6 +239,18 @@ module ccc
     // I3C_DIRECT_GETDCR
     input logic [7:0] get_dcr_i,
 
+    // Get virtual device Provisioned ID
+    // I3C_DIRECT_GETPID
+    input logic [47:0] virtual_get_pid_i,
+
+    // Get virtual device Bus Characteristics Register
+    // I3C_DIRECT_GETBCR
+    input logic [7:0] virtual_get_bcr_i,
+
+    // Get virtual Device Characteristics Register
+    // I3C_DIRECT_GETDCR
+    input logic [7:0] virtual_get_dcr_i,
+
     // Get Device Status
     // [15:8] Reserved for vendor-specific meaning, expected to be unused.
     // TODO: Bits 7:6 are tied to '11 until the Handoff procedure is fully implemented.
@@ -1023,10 +1034,14 @@ module ccc
   ccc_entdaa xccc_entdaa (
     .clk_i,  // Clock
     .rst_ni, // Async reset, active low
-    .id_i,
+    .id_i(get_pid_i),
     .bcr_i(get_bcr_i),
     .dcr_i(get_dcr_i),
 
+    .virtual_id_i(virtual_get_pid_i),
+    .virtual_bcr_i(virtual_get_bcr_i),
+    .virtual_dcr_i(virtual_get_dcr_i),
+
     .start_daa_i(entdaa_o),
     .done_daa_o(entdaa_done),
 

src/ctrl/ccc_entdaa.sv

@@ -8,6 +8,10 @@ module ccc_entdaa
     input logic [7:0] dcr_i,
     input logic [7:0] bcr_i,
 
+    input logic [47:0] virtual_id_i,
+    input logic [7:0] virtual_dcr_i,
+    input logic [7:0] virtual_bcr_i,
+
     input logic start_daa_i,
     output logic done_daa_o,
 

src/ctrl/configuration.sv

@@ -35,6 +35,9 @@ module configuration (
     output logic [47:0] pid_o,  // Target ID
     output logic [ 7:0] bcr_o,  // Bus Characteristics Register
     output logic [ 7:0] dcr_o,  // Device Characteristics Register
+    output logic [47:0] virtual_pid_o,  // Target ID
+    output logic [ 7:0] virtual_bcr_o,  // Bus Characteristics Register
+    output logic [ 7:0] virtual_dcr_o,  // Device Characteristics Register
 
     // Output effective target address (static or dynamic or recovery)
     output logic [6:0] target_sta_addr_o,
@@ -180,6 +183,18 @@ module configuration (
   };
 
   assign dcr_o = hwif_out_i.I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_CHAR.DCR.value;
+  assign virtual_pid_o = {
+    hwif_out_i.I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_CHAR.PID_HI.value,
+    1'b0,
+    hwif_out_i.I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_PID_LO.PID_LO.value
+  };
+
+  assign virtual_bcr_o = {
+    hwif_out_i.I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_CHAR.BCR_FIXED.value,
+    hwif_out_i.I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_CHAR.BCR_VAR.value
+  };
+
+  assign virtual_dcr_o = hwif_out_i.I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_CHAR.DCR.value;
   assign daa_unique_response_o = {pid_o, bcr_o, dcr_o};
 
   assign target_ibi_addr_o = target_dyn_addr_valid_o ? target_dyn_addr_o : target_sta_addr_o;

src/ctrl/controller.sv

@@ -62,8 +62,6 @@ module controller
 ) (
     input logic clk_i,
     input logic rst_ni,
-    input logic [47:0] id_i,
-
     // Interface to SDA/SCL
     input  logic scl_i,
     input  logic sda_i,
@@ -268,6 +266,9 @@ module controller
   logic [47:0] pid;
   logic [7:0] bcr;
   logic [7:0] dcr;
+  logic [47:0] virtual_pid;
+  logic [7:0] virtual_bcr;
+  logic [7:0] virtual_dcr;
   logic [6:0] target_sta_addr;
   logic target_sta_addr_valid;
   logic [6:0] target_dyn_addr;
@@ -354,6 +355,9 @@ module controller
       .pid_o                           (pid),
       .bcr_o                           (bcr),
       .dcr_o                           (dcr),
+      .virtual_pid_o                   (virtual_pid),
+      .virtual_bcr_o                   (virtual_bcr),
+      .virtual_dcr_o                   (virtual_dcr),
       .target_sta_addr_o               (target_sta_addr),
       .target_sta_addr_valid_o         (target_sta_addr_valid),
       .target_dyn_addr_o               (target_dyn_addr),
@@ -458,7 +462,6 @@ module controller
   controller_standby xcontroller_standby (
       .clk_i(clk_i),
       .rst_ni(rst_ni),
-      .id_i(id_i),
       .ctrl_bus_i(ctrl_bus_i[2:3]),
       .ctrl_scl_o(ctrl_scl_o[2:3]),
       .ctrl_sda_o(ctrl_sda_o[2:3]),
@@ -533,6 +536,9 @@ module controller
       .pid_i(pid),
       .bcr_i(bcr),
       .dcr_i(dcr),
+      .virtual_pid_i(virtual_pid),
+      .virtual_bcr_i(virtual_bcr),
+      .virtual_dcr_i(virtual_dcr),
       .target_sta_addr_i(target_sta_addr),
       .target_sta_addr_valid_i(target_sta_addr_valid),
       .target_dyn_addr_i(target_dyn_addr),

src/ctrl/controller_standby.sv

@@ -30,8 +30,6 @@ module controller_standby
 ) (
     input logic clk_i,
     input logic rst_ni,
-    input logic [47:0] id_i,
-
     // Interface to SDA/SCL
     input bus_state_t ctrl_bus_i[2],
     output logic ctrl_scl_o[2],
@@ -125,6 +123,9 @@ module controller_standby
     input logic [47:0] pid_i,
     input logic [7:0] bcr_i,
     input logic [7:0] dcr_i,
+    input logic [47:0] virtual_pid_i,
+    input logic [7:0] virtual_bcr_i,
+    input logic [7:0] virtual_dcr_i,
     input logic [6:0] target_sta_addr_i,
     input logic target_sta_addr_valid_i,
     input logic [6:0] target_dyn_addr_i,
@@ -385,7 +386,6 @@ module controller_standby
   ) xcontroller_standby_i3c (
       .clk_i(clk_i),
       .rst_ni(rst_ni),
-      .id_i(id_i),
       .ctrl_bus_i(ctrl_bus_i[1]),
       .ctrl_scl_o(ctrl_scl_o[1]),
       .ctrl_sda_o(ctrl_sda_o[1]),
@@ -428,6 +428,9 @@ module controller_standby
       .pid_i(pid_i),
       .bcr_i(bcr_i),
       .dcr_i(dcr_i),
+      .virtual_pid_i(virtual_pid_i),
+      .virtual_bcr_i(virtual_bcr_i),
+      .virtual_dcr_i(virtual_dcr_i),
       .target_sta_addr_i(target_sta_addr_i),
       .target_sta_addr_valid_i(target_sta_addr_valid_i),
       .target_dyn_addr_i(target_dyn_addr_i),

src/ctrl/controller_standby_i3c.sv

@@ -16,7 +16,6 @@ module controller_standby_i3c
 ) (
     input logic clk_i,
     input logic rst_ni,
-    input logic [47:0] id_i,
 
     // Interface to SDA/SCL
     input bus_state_t ctrl_bus_i,
@@ -77,6 +76,9 @@ module controller_standby_i3c
     input logic [47:0] pid_i,
     input logic [7:0] bcr_i,
     input logic [7:0] dcr_i,
+    input logic [47:0] virtual_pid_i,
+    input logic [7:0] virtual_bcr_i,
+    input logic [7:0] virtual_dcr_i,
     input logic [6:0] target_sta_addr_i,
     input logic target_sta_addr_valid_i,
     input logic [6:0] target_dyn_addr_i,
@@ -469,7 +471,6 @@ module controller_standby_i3c
   ccc xccc (
       .clk_i,
       .rst_ni,
-      .id_i,
       .arbitration_lost_i,
       .ccc_i                     (ccc),
       .ccc_valid_i               (ccc_valid),
@@ -533,6 +534,9 @@ module controller_standby_i3c
       .get_pid_i                 (pid_i),
       .get_bcr_i                 (bcr_i),
       .get_dcr_i                 (dcr_i),
+      .virtual_get_pid_i         (virtual_pid_i),
+      .virtual_get_bcr_i         (virtual_bcr_i),
+      .virtual_get_dcr_i         (virtual_dcr_i),
       .get_status_fmt1_i         (get_status_fmt1_i),
       .get_acccr_i               (get_acccr),
       .set_brgtgt_o              (set_brgtgt),

src/i3c.sv

@@ -102,7 +102,6 @@ module i3c
 ) (
     input clk_i,  // clock
     input rst_ni, // active low reset
-    input logic [47:0] id_i,
 
 `ifdef I3C_USE_AHB
     // AHB-Lite interface
@@ -565,7 +564,6 @@ module i3c
   ) xcontroller (
       .clk_i (clk_i),
       .rst_ni(rst_ni),
-      .id_i  (id_i),
 
       .scl_i(phy2ctrl_scl),
       .sda_i(phy2ctrl_sda),

src/i3c_wrapper.sv

@@ -22,7 +22,6 @@ module i3c_wrapper #(
 ) (
     input clk_i,  // clock
     input rst_ni, // active low reset
-    input logic [47:0] id_i,
 
 `ifdef I3C_USE_AHB
     // AHB-Lite interface
@@ -163,7 +162,6 @@ module i3c_wrapper #(
   ) i3c (
       .clk_i,
       .rst_ni,
-      .id_i,
 
 `ifdef I3C_USE_AHB
       .haddr_i,