@@ -52,7 +52,7 @@ async def common_procedure(tb: I3CTopTestInterface):
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return core_config
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- async def boot_init (tb : I3CTopTestInterface , timings = None ):
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+ async def boot_init (tb : I3CTopTestInterface , timings = None , verify = False ):
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"""
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Boot sequence model should match the description in "Boot and Initialization" chapter of the documentation.
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@@ -79,7 +79,7 @@ async def boot_init(tb: I3CTopTestInterface, timings=None):
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await setup_hci_thresholds (tb )
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# Start the device
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- await umbrella_stby_init (tb )
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+ await umbrella_stby_init (tb , verify )
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async def check_version (tb ):
@@ -193,7 +193,7 @@ async def define_supported_ccc(tb):
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pass
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- async def umbrella_stby_init (tb ):
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+ async def umbrella_stby_init (tb , verify = False ):
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"""
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Set the BCR bits and the DCR value in register STBY_CR_DEVICE_CHAR.
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@@ -253,6 +253,48 @@ async def umbrella_stby_init(tb):
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# 1,
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# )
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+ # Check if CSRs have been set properly
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+ if verify :
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+ mode = await tb .read_csr_field (
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+ tb .reg_map .I3C_EC .STDBYCTRLMODE .STBY_CR_CONTROL .base_addr ,
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+ tb .reg_map .I3C_EC .STDBYCTRLMODE .STBY_CR_CONTROL .STBY_CR_ENABLE_INIT ,
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+ )
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+ assert mode == 2
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+
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+ # Set static address and valid
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+ static_addr = await tb .read_csr_field (
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+ tb .reg_map .I3C_EC .STDBYCTRLMODE .STBY_CR_DEVICE_ADDR .base_addr ,
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+ tb .reg_map .I3C_EC .STDBYCTRLMODE .STBY_CR_DEVICE_ADDR .STATIC_ADDR ,
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+ )
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+ assert static_addr == 0x5A
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+
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+ static_addr_valid = await tb .read_csr_field (
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+ tb .reg_map .I3C_EC .STDBYCTRLMODE .STBY_CR_DEVICE_ADDR .base_addr ,
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+ tb .reg_map .I3C_EC .STDBYCTRLMODE .STBY_CR_DEVICE_ADDR .STATIC_ADDR_VALID ,
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+ )
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+ assert static_addr_valid == 0x1
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+
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+ # Set static address and valid for virtual device
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+ virt_static_addr = await tb .read_csr_field (
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+ tb .reg_map .I3C_EC .STDBYCTRLMODE .STBY_CR_VIRT_DEVICE_ADDR .base_addr ,
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+ tb .reg_map .I3C_EC .STDBYCTRLMODE .STBY_CR_VIRT_DEVICE_ADDR .VIRT_STATIC_ADDR ,
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+ )
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+ assert virt_static_addr == 0x5B
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+
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+ virt_static_addr_valid = await tb .read_csr_field (
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+ tb .reg_map .I3C_EC .STDBYCTRLMODE .STBY_CR_VIRT_DEVICE_ADDR .base_addr ,
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+ tb .reg_map .I3C_EC .STDBYCTRLMODE .STBY_CR_VIRT_DEVICE_ADDR .VIRT_STATIC_ADDR_VALID ,
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+ 0x1 ,
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+ )
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+ assert virt_static_addr_valid == 0x1
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+
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+ # Enable Target Interface
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+ tgt_en = await tb .read_csr_field (
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+ tb .reg_map .I3C_EC .STDBYCTRLMODE .STBY_CR_CONTROL .base_addr ,
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+ tb .reg_map .I3C_EC .STDBYCTRLMODE .STBY_CR_CONTROL .TARGET_XACT_ENABLE ,
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+ )
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+ assert tgt_en == 1
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+
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async def tti_init (tb ):
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"""
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