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robertszczepanskikgugala
robertszczepanski
authored and
kgugala
committed
Add support for I3C Core bypass via CSRs
1 parent aa6bdc9 commit d6485f3

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22 files changed

+1404
-293
lines changed

22 files changed

+1404
-293
lines changed

‎src/csr/I3CCSR.sv‎

Lines changed: 150 additions & 40 deletions
Large diffs are not rendered by default.

‎src/csr/I3CCSR_covergroups.svh‎

Lines changed: 16 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -2429,8 +2429,8 @@
24292429

24302430
endgroup
24312431

2432-
/*----------------------- I3CCSR__I3C_EC__SOCMGMTIF__SOC_MGMT_RSVD_0 COVERGROUPS -----------------------*/
2433-
covergroup I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_0_bit_cg with function sample(input bit reg_bit);
2432+
/*----------------------- I3CCSR__I3C_EC__SOCMGMTIF__REC_INTF_CFG COVERGROUPS -----------------------*/
2433+
covergroup I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_CFG_bit_cg with function sample(input bit reg_bit);
24342434
option.per_instance = 1;
24352435
reg_bit_cp : coverpoint reg_bit {
24362436
bins value[2] = {0,1};
@@ -2441,16 +2441,18 @@
24412441
}
24422442

24432443
endgroup
2444-
covergroup I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_0_fld_cg with function sample(
2445-
input bit [32-1:0] PLACEHOLDER
2444+
covergroup I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_CFG_fld_cg with function sample(
2445+
input bit [1-1:0] REC_INTF_BYPASS,
2446+
input bit [1-1:0] REC_PAYLOAD_DONE
24462447
);
24472448
option.per_instance = 1;
2448-
PLACEHOLDER_cp : coverpoint PLACEHOLDER;
2449+
REC_INTF_BYPASS_cp : coverpoint REC_INTF_BYPASS;
2450+
REC_PAYLOAD_DONE_cp : coverpoint REC_PAYLOAD_DONE;
24492451

24502452
endgroup
24512453

2452-
/*----------------------- I3CCSR__I3C_EC__SOCMGMTIF__SOC_MGMT_RSVD_1 COVERGROUPS -----------------------*/
2453-
covergroup I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_1_bit_cg with function sample(input bit reg_bit);
2454+
/*----------------------- I3CCSR__I3C_EC__SOCMGMTIF__REC_INTF_REG_W1C_ACCESS COVERGROUPS -----------------------*/
2455+
covergroup I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS_bit_cg with function sample(input bit reg_bit);
24542456
option.per_instance = 1;
24552457
reg_bit_cp : coverpoint reg_bit {
24562458
bins value[2] = {0,1};
@@ -2461,11 +2463,15 @@
24612463
}
24622464

24632465
endgroup
2464-
covergroup I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_1_fld_cg with function sample(
2465-
input bit [32-1:0] PLACEHOLDER
2466+
covergroup I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS_fld_cg with function sample(
2467+
input bit [8-1:0] DEVICE_RESET_CTRL,
2468+
input bit [8-1:0] RECOVERY_CTRL_ACTIVATE_REC_IMG,
2469+
input bit [8-1:0] INDIRECT_FIFO_CTRL_RESET
24662470
);
24672471
option.per_instance = 1;
2468-
PLACEHOLDER_cp : coverpoint PLACEHOLDER;
2472+
DEVICE_RESET_CTRL_cp : coverpoint DEVICE_RESET_CTRL;
2473+
RECOVERY_CTRL_ACTIVATE_REC_IMG_cp : coverpoint RECOVERY_CTRL_ACTIVATE_REC_IMG;
2474+
INDIRECT_FIFO_CTRL_RESET_cp : coverpoint INDIRECT_FIFO_CTRL_RESET;
24692475

24702476
endgroup
24712477

‎src/csr/I3CCSR_pkg.sv‎

Lines changed: 64 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1231,6 +1231,41 @@ package I3CCSR_pkg;
12311231
I3CCSR__I3C_EC__TTI__QUEUE_THLD_CTRL__in_t QUEUE_THLD_CTRL;
12321232
} I3CCSR__I3C_EC__TTI__in_t;
12331233

1234+
typedef struct packed{
1235+
logic next;
1236+
logic we;
1237+
} I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_CFG__REC_PAYLOAD_DONE__in_t;
1238+
1239+
typedef struct packed{
1240+
I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_CFG__REC_PAYLOAD_DONE__in_t REC_PAYLOAD_DONE;
1241+
} I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_CFG__in_t;
1242+
1243+
typedef struct packed{
1244+
logic [7:0] next;
1245+
logic we;
1246+
} I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS__DEVICE_RESET_CTRL__in_t;
1247+
1248+
typedef struct packed{
1249+
logic [7:0] next;
1250+
logic we;
1251+
} I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS__RECOVERY_CTRL_ACTIVATE_REC_IMG__in_t;
1252+
1253+
typedef struct packed{
1254+
logic [7:0] next;
1255+
logic we;
1256+
} I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS__INDIRECT_FIFO_CTRL_RESET__in_t;
1257+
1258+
typedef struct packed{
1259+
I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS__DEVICE_RESET_CTRL__in_t DEVICE_RESET_CTRL;
1260+
I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS__RECOVERY_CTRL_ACTIVATE_REC_IMG__in_t RECOVERY_CTRL_ACTIVATE_REC_IMG;
1261+
I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS__INDIRECT_FIFO_CTRL_RESET__in_t INDIRECT_FIFO_CTRL_RESET;
1262+
} I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS__in_t;
1263+
1264+
typedef struct packed{
1265+
I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_CFG__in_t REC_INTF_CFG;
1266+
I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS__in_t REC_INTF_REG_W1C_ACCESS;
1267+
} I3CCSR__I3C_EC__SoCMgmtIf__in_t;
1268+
12341269
typedef struct packed{
12351270
logic [1:0] next;
12361271
logic we;
@@ -1248,6 +1283,7 @@ package I3CCSR_pkg;
12481283
I3CCSR__I3C_EC__SecFwRecoveryIf__in_t SecFwRecoveryIf;
12491284
I3CCSR__I3C_EC__StdbyCtrlMode__in_t StdbyCtrlMode;
12501285
I3CCSR__I3C_EC__TTI__in_t TTI;
1286+
I3CCSR__I3C_EC__SoCMgmtIf__in_t SoCMgmtIf;
12511287
I3CCSR__I3C_EC__CtrlCfg__in_t CtrlCfg;
12521288
} I3CCSR__I3C_EC__in_t;
12531289

@@ -2985,20 +3021,38 @@ package I3CCSR_pkg;
29853021
} I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_STATUS__out_t;
29863022

29873023
typedef struct packed{
2988-
logic [31:0] value;
2989-
} I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_0__PLACEHOLDER__out_t;
3024+
logic value;
3025+
} I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_CFG__REC_INTF_BYPASS__out_t;
29903026

29913027
typedef struct packed{
2992-
I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_0__PLACEHOLDER__out_t PLACEHOLDER;
2993-
} I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_0__out_t;
3028+
logic value;
3029+
} I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_CFG__REC_PAYLOAD_DONE__out_t;
29943030

29953031
typedef struct packed{
2996-
logic [31:0] value;
2997-
} I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_1__PLACEHOLDER__out_t;
3032+
I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_CFG__REC_INTF_BYPASS__out_t REC_INTF_BYPASS;
3033+
I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_CFG__REC_PAYLOAD_DONE__out_t REC_PAYLOAD_DONE;
3034+
} I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_CFG__out_t;
3035+
3036+
typedef struct packed{
3037+
logic [7:0] value;
3038+
logic swmod;
3039+
} I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS__DEVICE_RESET_CTRL__out_t;
3040+
3041+
typedef struct packed{
3042+
logic [7:0] value;
3043+
logic swmod;
3044+
} I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS__RECOVERY_CTRL_ACTIVATE_REC_IMG__out_t;
3045+
3046+
typedef struct packed{
3047+
logic [7:0] value;
3048+
logic swmod;
3049+
} I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS__INDIRECT_FIFO_CTRL_RESET__out_t;
29983050

29993051
typedef struct packed{
3000-
I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_1__PLACEHOLDER__out_t PLACEHOLDER;
3001-
} I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_1__out_t;
3052+
I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS__DEVICE_RESET_CTRL__out_t DEVICE_RESET_CTRL;
3053+
I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS__RECOVERY_CTRL_ACTIVATE_REC_IMG__out_t RECOVERY_CTRL_ACTIVATE_REC_IMG;
3054+
I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS__INDIRECT_FIFO_CTRL_RESET__out_t INDIRECT_FIFO_CTRL_RESET;
3055+
} I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS__out_t;
30023056

30033057
typedef struct packed{
30043058
logic [31:0] value;
@@ -3193,8 +3247,8 @@ package I3CCSR_pkg;
31933247
I3CCSR__I3C_EC__SoCMgmtIf__EXTCAP_HEADER__out_t EXTCAP_HEADER;
31943248
I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_CONTROL__out_t SOC_MGMT_CONTROL;
31953249
I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_STATUS__out_t SOC_MGMT_STATUS;
3196-
I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_0__out_t SOC_MGMT_RSVD_0;
3197-
I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_1__out_t SOC_MGMT_RSVD_1;
3250+
I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_CFG__out_t REC_INTF_CFG;
3251+
I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS__out_t REC_INTF_REG_W1C_ACCESS;
31983252
I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_2__out_t SOC_MGMT_RSVD_2;
31993253
I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_3__out_t SOC_MGMT_RSVD_3;
32003254
I3CCSR__I3C_EC__SoCMgmtIf__SOC_PAD_CONF__out_t SOC_PAD_CONF;

‎src/csr/I3CCSR_sample.svh‎

Lines changed: 20 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -2914,53 +2914,59 @@
29142914
end
29152915
endfunction
29162916

2917-
/*----------------------- I3CCSR__I3C_EC__SOCMGMTIF__SOC_MGMT_RSVD_0 SAMPLE FUNCTIONS -----------------------*/
2918-
function void I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_0::sample(uvm_reg_data_t data,
2917+
/*----------------------- I3CCSR__I3C_EC__SOCMGMTIF__REC_INTF_CFG SAMPLE FUNCTIONS -----------------------*/
2918+
function void I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_CFG::sample(uvm_reg_data_t data,
29192919
uvm_reg_data_t byte_en,
29202920
bit is_read,
29212921
uvm_reg_map map);
29222922
m_current = get();
29232923
m_data = data;
29242924
m_is_read = is_read;
29252925
if (get_coverage(UVM_CVR_REG_BITS)) begin
2926-
foreach(PLACEHOLDER_bit_cg[bt]) this.PLACEHOLDER_bit_cg[bt].sample(data[0 + bt]);
2926+
foreach(REC_INTF_BYPASS_bit_cg[bt]) this.REC_INTF_BYPASS_bit_cg[bt].sample(data[0 + bt]);
2927+
foreach(REC_PAYLOAD_DONE_bit_cg[bt]) this.REC_PAYLOAD_DONE_bit_cg[bt].sample(data[1 + bt]);
29272928
end
29282929
if (get_coverage(UVM_CVR_FIELD_VALS)) begin
2929-
this.fld_cg.sample( data[31:0]/*PLACEHOLDER*/ );
2930+
this.fld_cg.sample( data[0:0]/*REC_INTF_BYPASS*/ , data[1:1]/*REC_PAYLOAD_DONE*/ );
29302931
end
29312932
endfunction
29322933

2933-
function void I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_0::sample_values();
2934+
function void I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_CFG::sample_values();
29342935
if (get_coverage(UVM_CVR_REG_BITS)) begin
2935-
foreach(PLACEHOLDER_bit_cg[bt]) this.PLACEHOLDER_bit_cg[bt].sample(PLACEHOLDER.get_mirrored_value() >> bt);
2936+
foreach(REC_INTF_BYPASS_bit_cg[bt]) this.REC_INTF_BYPASS_bit_cg[bt].sample(REC_INTF_BYPASS.get_mirrored_value() >> bt);
2937+
foreach(REC_PAYLOAD_DONE_bit_cg[bt]) this.REC_PAYLOAD_DONE_bit_cg[bt].sample(REC_PAYLOAD_DONE.get_mirrored_value() >> bt);
29362938
end
29372939
if (get_coverage(UVM_CVR_FIELD_VALS)) begin
2938-
this.fld_cg.sample( PLACEHOLDER.get_mirrored_value() );
2940+
this.fld_cg.sample( REC_INTF_BYPASS.get_mirrored_value() , REC_PAYLOAD_DONE.get_mirrored_value() );
29392941
end
29402942
endfunction
29412943

2942-
/*----------------------- I3CCSR__I3C_EC__SOCMGMTIF__SOC_MGMT_RSVD_1 SAMPLE FUNCTIONS -----------------------*/
2943-
function void I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_1::sample(uvm_reg_data_t data,
2944+
/*----------------------- I3CCSR__I3C_EC__SOCMGMTIF__REC_INTF_REG_W1C_ACCESS SAMPLE FUNCTIONS -----------------------*/
2945+
function void I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS::sample(uvm_reg_data_t data,
29442946
uvm_reg_data_t byte_en,
29452947
bit is_read,
29462948
uvm_reg_map map);
29472949
m_current = get();
29482950
m_data = data;
29492951
m_is_read = is_read;
29502952
if (get_coverage(UVM_CVR_REG_BITS)) begin
2951-
foreach(PLACEHOLDER_bit_cg[bt]) this.PLACEHOLDER_bit_cg[bt].sample(data[0 + bt]);
2953+
foreach(DEVICE_RESET_CTRL_bit_cg[bt]) this.DEVICE_RESET_CTRL_bit_cg[bt].sample(data[0 + bt]);
2954+
foreach(RECOVERY_CTRL_ACTIVATE_REC_IMG_bit_cg[bt]) this.RECOVERY_CTRL_ACTIVATE_REC_IMG_bit_cg[bt].sample(data[8 + bt]);
2955+
foreach(INDIRECT_FIFO_CTRL_RESET_bit_cg[bt]) this.INDIRECT_FIFO_CTRL_RESET_bit_cg[bt].sample(data[16 + bt]);
29522956
end
29532957
if (get_coverage(UVM_CVR_FIELD_VALS)) begin
2954-
this.fld_cg.sample( data[31:0]/*PLACEHOLDER*/ );
2958+
this.fld_cg.sample( data[7:0]/*DEVICE_RESET_CTRL*/ , data[15:8]/*RECOVERY_CTRL_ACTIVATE_REC_IMG*/ , data[23:16]/*INDIRECT_FIFO_CTRL_RESET*/ );
29552959
end
29562960
endfunction
29572961

2958-
function void I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_1::sample_values();
2962+
function void I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS::sample_values();
29592963
if (get_coverage(UVM_CVR_REG_BITS)) begin
2960-
foreach(PLACEHOLDER_bit_cg[bt]) this.PLACEHOLDER_bit_cg[bt].sample(PLACEHOLDER.get_mirrored_value() >> bt);
2964+
foreach(DEVICE_RESET_CTRL_bit_cg[bt]) this.DEVICE_RESET_CTRL_bit_cg[bt].sample(DEVICE_RESET_CTRL.get_mirrored_value() >> bt);
2965+
foreach(RECOVERY_CTRL_ACTIVATE_REC_IMG_bit_cg[bt]) this.RECOVERY_CTRL_ACTIVATE_REC_IMG_bit_cg[bt].sample(RECOVERY_CTRL_ACTIVATE_REC_IMG.get_mirrored_value() >> bt);
2966+
foreach(INDIRECT_FIFO_CTRL_RESET_bit_cg[bt]) this.INDIRECT_FIFO_CTRL_RESET_bit_cg[bt].sample(INDIRECT_FIFO_CTRL_RESET.get_mirrored_value() >> bt);
29612967
end
29622968
if (get_coverage(UVM_CVR_FIELD_VALS)) begin
2963-
this.fld_cg.sample( PLACEHOLDER.get_mirrored_value() );
2969+
this.fld_cg.sample( DEVICE_RESET_CTRL.get_mirrored_value() , RECOVERY_CTRL_ACTIVATE_REC_IMG.get_mirrored_value() , INDIRECT_FIFO_CTRL_RESET.get_mirrored_value() );
29642970
end
29652971
endfunction
29662972

‎src/csr/I3CCSR_uvm.sv‎

Lines changed: 45 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -4723,17 +4723,19 @@ package I3CCSR_uvm;
47234723
endfunction : build
47244724
endclass : I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_STATUS
47254725

4726-
// Reg - I3CCSR.I3C_EC.SoCMgmtIf.SOC_MGMT_RSVD_0
4727-
class I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_0 extends uvm_reg;
4726+
// Reg - I3CCSR.I3C_EC.SoCMgmtIf.REC_INTF_CFG
4727+
class I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_CFG extends uvm_reg;
47284728
protected uvm_reg_data_t m_current;
47294729
protected uvm_reg_data_t m_data;
47304730
protected bit m_is_read;
47314731

4732-
I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_0_bit_cg PLACEHOLDER_bit_cg[32];
4733-
I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_0_fld_cg fld_cg;
4734-
rand uvm_reg_field PLACEHOLDER;
4732+
I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_CFG_bit_cg REC_INTF_BYPASS_bit_cg[1];
4733+
I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_CFG_bit_cg REC_PAYLOAD_DONE_bit_cg[1];
4734+
I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_CFG_fld_cg fld_cg;
4735+
rand uvm_reg_field REC_INTF_BYPASS;
4736+
rand uvm_reg_field REC_PAYLOAD_DONE;
47354737

4736-
function new(string name = "I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_0");
4738+
function new(string name = "I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_CFG");
47374739
super.new(name, 32, build_coverage(UVM_CVR_ALL));
47384740
endfunction : new
47394741
extern virtual function void sample_values();
@@ -4743,27 +4745,34 @@ package I3CCSR_uvm;
47434745
uvm_reg_map map);
47444746

47454747
virtual function void build();
4746-
this.PLACEHOLDER = new("PLACEHOLDER");
4747-
this.PLACEHOLDER.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
4748+
this.REC_INTF_BYPASS = new("REC_INTF_BYPASS");
4749+
this.REC_INTF_BYPASS.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
4750+
this.REC_PAYLOAD_DONE = new("REC_PAYLOAD_DONE");
4751+
this.REC_PAYLOAD_DONE.configure(this, 1, 1, "RW", 1, 'h0, 1, 1, 0);
47484752
if (has_coverage(UVM_CVR_REG_BITS)) begin
4749-
foreach(PLACEHOLDER_bit_cg[bt]) PLACEHOLDER_bit_cg[bt] = new();
4753+
foreach(REC_INTF_BYPASS_bit_cg[bt]) REC_INTF_BYPASS_bit_cg[bt] = new();
4754+
foreach(REC_PAYLOAD_DONE_bit_cg[bt]) REC_PAYLOAD_DONE_bit_cg[bt] = new();
47504755
end
47514756
if (has_coverage(UVM_CVR_FIELD_VALS))
47524757
fld_cg = new();
47534758
endfunction : build
4754-
endclass : I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_0
4759+
endclass : I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_CFG
47554760

4756-
// Reg - I3CCSR.I3C_EC.SoCMgmtIf.SOC_MGMT_RSVD_1
4757-
class I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_1 extends uvm_reg;
4761+
// Reg - I3CCSR.I3C_EC.SoCMgmtIf.REC_INTF_REG_W1C_ACCESS
4762+
class I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS extends uvm_reg;
47584763
protected uvm_reg_data_t m_current;
47594764
protected uvm_reg_data_t m_data;
47604765
protected bit m_is_read;
47614766

4762-
I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_1_bit_cg PLACEHOLDER_bit_cg[32];
4763-
I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_1_fld_cg fld_cg;
4764-
rand uvm_reg_field PLACEHOLDER;
4767+
I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS_bit_cg DEVICE_RESET_CTRL_bit_cg[8];
4768+
I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS_bit_cg RECOVERY_CTRL_ACTIVATE_REC_IMG_bit_cg[8];
4769+
I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS_bit_cg INDIRECT_FIFO_CTRL_RESET_bit_cg[8];
4770+
I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS_fld_cg fld_cg;
4771+
rand uvm_reg_field DEVICE_RESET_CTRL;
4772+
rand uvm_reg_field RECOVERY_CTRL_ACTIVATE_REC_IMG;
4773+
rand uvm_reg_field INDIRECT_FIFO_CTRL_RESET;
47654774

4766-
function new(string name = "I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_1");
4775+
function new(string name = "I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS");
47674776
super.new(name, 32, build_coverage(UVM_CVR_ALL));
47684777
endfunction : new
47694778
extern virtual function void sample_values();
@@ -4773,15 +4782,21 @@ package I3CCSR_uvm;
47734782
uvm_reg_map map);
47744783

47754784
virtual function void build();
4776-
this.PLACEHOLDER = new("PLACEHOLDER");
4777-
this.PLACEHOLDER.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
4785+
this.DEVICE_RESET_CTRL = new("DEVICE_RESET_CTRL");
4786+
this.DEVICE_RESET_CTRL.configure(this, 8, 0, "RW", 1, 'h0, 1, 1, 0);
4787+
this.RECOVERY_CTRL_ACTIVATE_REC_IMG = new("RECOVERY_CTRL_ACTIVATE_REC_IMG");
4788+
this.RECOVERY_CTRL_ACTIVATE_REC_IMG.configure(this, 8, 8, "RW", 1, 'h0, 1, 1, 0);
4789+
this.INDIRECT_FIFO_CTRL_RESET = new("INDIRECT_FIFO_CTRL_RESET");
4790+
this.INDIRECT_FIFO_CTRL_RESET.configure(this, 8, 16, "RW", 1, 'h0, 1, 1, 0);
47784791
if (has_coverage(UVM_CVR_REG_BITS)) begin
4779-
foreach(PLACEHOLDER_bit_cg[bt]) PLACEHOLDER_bit_cg[bt] = new();
4792+
foreach(DEVICE_RESET_CTRL_bit_cg[bt]) DEVICE_RESET_CTRL_bit_cg[bt] = new();
4793+
foreach(RECOVERY_CTRL_ACTIVATE_REC_IMG_bit_cg[bt]) RECOVERY_CTRL_ACTIVATE_REC_IMG_bit_cg[bt] = new();
4794+
foreach(INDIRECT_FIFO_CTRL_RESET_bit_cg[bt]) INDIRECT_FIFO_CTRL_RESET_bit_cg[bt] = new();
47804795
end
47814796
if (has_coverage(UVM_CVR_FIELD_VALS))
47824797
fld_cg = new();
47834798
endfunction : build
4784-
endclass : I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_1
4799+
endclass : I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS
47854800

47864801
// Reg - I3CCSR.I3C_EC.SoCMgmtIf.SOC_MGMT_RSVD_2
47874802
class I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_2 extends uvm_reg;
@@ -5373,8 +5388,8 @@ package I3CCSR_uvm;
53735388
rand I3CCSR__I3C_EC__SoCMgmtIf__EXTCAP_HEADER EXTCAP_HEADER;
53745389
rand I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_CONTROL SOC_MGMT_CONTROL;
53755390
rand I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_STATUS SOC_MGMT_STATUS;
5376-
rand I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_0 SOC_MGMT_RSVD_0;
5377-
rand I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_1 SOC_MGMT_RSVD_1;
5391+
rand I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_CFG REC_INTF_CFG;
5392+
rand I3CCSR__I3C_EC__SoCMgmtIf__REC_INTF_REG_W1C_ACCESS REC_INTF_REG_W1C_ACCESS;
53785393
rand I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_2 SOC_MGMT_RSVD_2;
53795394
rand I3CCSR__I3C_EC__SoCMgmtIf__SOC_MGMT_RSVD_3 SOC_MGMT_RSVD_3;
53805395
rand I3CCSR__I3C_EC__SoCMgmtIf__SOC_PAD_CONF SOC_PAD_CONF;
@@ -5415,16 +5430,16 @@ package I3CCSR_uvm;
54155430

54165431
this.SOC_MGMT_STATUS.build();
54175432
this.default_map.add_reg(this.SOC_MGMT_STATUS, 'h8);
5418-
this.SOC_MGMT_RSVD_0 = new("SOC_MGMT_RSVD_0");
5419-
this.SOC_MGMT_RSVD_0.configure(this);
5433+
this.REC_INTF_CFG = new("REC_INTF_CFG");
5434+
this.REC_INTF_CFG.configure(this);
54205435

5421-
this.SOC_MGMT_RSVD_0.build();
5422-
this.default_map.add_reg(this.SOC_MGMT_RSVD_0, 'hc);
5423-
this.SOC_MGMT_RSVD_1 = new("SOC_MGMT_RSVD_1");
5424-
this.SOC_MGMT_RSVD_1.configure(this);
5436+
this.REC_INTF_CFG.build();
5437+
this.default_map.add_reg(this.REC_INTF_CFG, 'hc);
5438+
this.REC_INTF_REG_W1C_ACCESS = new("REC_INTF_REG_W1C_ACCESS");
5439+
this.REC_INTF_REG_W1C_ACCESS.configure(this);
54255440

5426-
this.SOC_MGMT_RSVD_1.build();
5427-
this.default_map.add_reg(this.SOC_MGMT_RSVD_1, 'h10);
5441+
this.REC_INTF_REG_W1C_ACCESS.build();
5442+
this.default_map.add_reg(this.REC_INTF_REG_W1C_ACCESS, 'h10);
54285443
this.SOC_MGMT_RSVD_2 = new("SOC_MGMT_RSVD_2");
54295444
this.SOC_MGMT_RSVD_2.configure(this);
54305445

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