Add test for I3C bypass during active I3C bus traffic

Author: robertszczepanski

src/ctrl/controller.sv

@@ -473,7 +473,6 @@ module controller
       .tx_desc_queue_rvalid_i(tti_tx_desc_queue_rvalid_i),
       .tx_desc_queue_rready_o(tti_tx_desc_queue_rready_o),
       .tx_desc_queue_rdata_i(tti_tx_desc_queue_rdata_i),
-      .rx_queue_full_i(tti_rx_queue_full_i),
       .rx_queue_depth_i(tti_rx_queue_depth_i),
       .rx_queue_start_thld_i(tti_rx_queue_start_thld_i),
       .rx_queue_start_thld_trig_i(tti_rx_queue_start_thld_trig_i),

src/ctrl/controller_standby.sv

@@ -60,7 +60,6 @@ module controller_standby
     input logic [TtiTxDescDataWidth-1:0] tx_desc_queue_rdata_i,
 
     // TTI: RX Data
-    input logic rx_queue_full_i,
     input logic [TtiRxFifoDepthWidth-1:0] rx_queue_depth_i,
     input logic [TtiRxThldWidth-1:0] rx_queue_start_thld_i,
     input logic rx_queue_start_thld_trig_i,
@@ -321,7 +320,6 @@ module controller_standby
       .tx_desc_queue_rvalid_i(tx_desc_queue_rvalid_i),
       .tx_desc_queue_rready_o(i2c_tx_desc_queue_rready_o),
       .tx_desc_queue_rdata_i(tx_desc_queue_rdata_i),
-      .rx_queue_full_i(rx_queue_full_i),
       .rx_queue_start_thld_i(rx_queue_start_thld_i),
       .rx_queue_start_thld_trig_i(rx_queue_start_thld_trig_i),
       .rx_queue_ready_thld_i(rx_queue_ready_thld_i),
@@ -391,7 +389,7 @@ module controller_standby
       .tx_desc_queue_rvalid_i(tx_desc_queue_rvalid_i),
       .tx_desc_queue_rready_o(i3c_tx_desc_queue_rready_o),
       .tx_desc_queue_rdata_i(tx_desc_queue_rdata_i),
-      .rx_queue_full_i(rx_queue_full_i),
+      .rx_queue_wready_i(rx_queue_wready_i),
       .rx_queue_wvalid_o(i3c_rx_queue_wvalid_o),
       .rx_queue_wdata_o(i3c_rx_queue_wdata_o),
       .rx_queue_flush_o(i3c_rx_queue_flush_o),

src/ctrl/controller_standby_i2c.sv

@@ -48,7 +48,6 @@ module controller_standby_i2c
     input logic [TtiTxDescDataWidth-1:0] tx_desc_queue_rdata_i,
 
     // TTI: RX Data
-    input logic rx_queue_full_i,
     input logic [TtiRxThldWidth-1:0] rx_queue_start_thld_i,
     input logic rx_queue_start_thld_trig_i,
     input logic [TtiRxThldWidth-1:0] rx_queue_ready_thld_i,

src/ctrl/controller_standby_i3c.sv

@@ -35,7 +35,7 @@ module controller_standby_i3c
     input logic [TtiTxDescDataWidth-1:0] tx_desc_queue_rdata_i,
 
     // TTI: RX Data
-    input logic rx_queue_full_i,
+    input logic rx_queue_wready_i,
     output logic rx_queue_wvalid_o,
     output logic rx_queue_flush_o,
     output logic [TtiRxDataWidth-1:0] rx_queue_wdata_o,
@@ -650,7 +650,7 @@ module controller_standby_i3c
       .rst_ni                    (rst_ni),
       .tti_rx_desc_queue_wvalid_o(rx_desc_queue_wvalid_o),
       .tti_rx_desc_queue_wdata_o (rx_desc_queue_wdata_o),
-      .tti_rx_queue_full_i       (rx_queue_full_i),
+      .tti_rx_queue_wready_i     (rx_queue_wready_i),
       .tti_rx_queue_wvalid_o     (rx_queue_wvalid_o),
       .tti_rx_queue_flush_o      (rx_queue_flush_o),
       .tti_rx_queue_wdata_o      (rx_queue_wdata_o),

src/ctrl/descriptor_rx.sv

@@ -36,7 +36,7 @@ module descriptor_rx #(
     output logic [TtiRxDescDataWidth-1:0] tti_rx_desc_queue_wdata_o,
 
     // TTI: RX Data
-    input logic tti_rx_queue_full_i,
+    input logic tti_rx_queue_wready_i,
     output logic tti_rx_queue_wvalid_o,
     output logic tti_rx_queue_flush_o,
     output logic [TtiRxDataWidth-1:0] tti_rx_queue_wdata_o,
@@ -91,7 +91,7 @@ module descriptor_rx #(
   end
 
   assign tti_rx_queue_wvalid_o = rx_byte_valid_i;
-  assign rx_byte_ready_o = ~tti_rx_queue_full_i;
+  assign rx_byte_ready_o = tti_rx_queue_wready_i;
   assign tti_rx_queue_wdata_o = rx_byte_i;
 
   assign rx_descriptor = {rx_error, {12{1'b0}}, byte_counter_q};

src/ctrl/i3c_target_fsm.sv

@@ -298,9 +298,23 @@ module i3c_target_fsm #(
   assign rx_overflow_err_o = ~rx_overflow_err_q & rx_overflow_err_r;
 
   // RX FIFO valid when we finish reading byte (leave RxPWriteData) and there was no parity error
-  assign rx_fifo_wvalid_o = (state_q == RxPWriteTbit) &
+  logic rx_fifo_wvalid;
+  assign rx_fifo_wvalid = (state_q == RxPWriteTbit) &
                             (state_d != RxPWriteTbit) &
                             ~(parity_err | rx_overflow_err_o);
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin : latch_rx_fifo_wvalid
+    if (~rst_ni) begin
+      rx_fifo_wvalid_o <= 1'b0;
+    end else begin
+      if (rx_fifo_wvalid) begin
+        rx_fifo_wvalid_o <= 1'b1;
+      end
+      if (rx_fifo_wvalid_o & rx_fifo_wready_i) begin
+        rx_fifo_wvalid_o <= 1'b0;
+      end
+    end
+  end
   // Last RX byte when we leave Private Write loop
   assign rx_last_byte_o = (state_q == RxPWriteData) & (state_d inside {RxFByte, Idle});
 

verification/cocotb/top/lib_i3c_top/test_bypass.py

@@ -4,15 +4,12 @@
 import random
 
 from bus2csr import dword2int, int2dword
+from cocotbext_i3c.i3c_controller import I3cController
+from cocotbext_i3c.i3c_target import I3CTarget
 from interface import I3CTopTestInterface
 
 import cocotb
-from cocotb.triggers import ClockCycles, Combine, Event, RisingEdge, Timer
-
-STATIC_ADDR = 0x5A
-VIRT_STATIC_ADDR = 0x5B
-DYNAMIC_ADDR = 0x52
-VIRT_DYNAMIC_ADDR = 0x53
+from cocotb.triggers import ClockCycles, Combine, Event, Join, RisingEdge, Timer
 
 
 async def write_to_indirect_fifo(tb, data=None, format="bytes"):
@@ -180,7 +177,7 @@ async def get_fifo_ptrs():
     assert (wrptr3, rdptr3) == (0, 0)
 
     # If top pointer is equal to 0, then FIFO should be full after write
-    fifo_full_at_top = (top_ptr == 0)
+    fifo_full_at_top = top_ptr == 0
 
     # Check empty/full progression
     assert (full0, empty0) == (False, True)
@@ -307,12 +304,18 @@ async def test_read(dut):
     assert recovery_data == device_id
 
     # Ensure there is access to rest of basic registers
-    hw_status = dword2int(await tb.read_csr(tb.reg_map.I3C_EC.SECFWRECOVERYIF.HW_STATUS.base_addr, 4))
+    hw_status = dword2int(
+        await tb.read_csr(tb.reg_map.I3C_EC.SECFWRECOVERYIF.HW_STATUS.base_addr, 4)
+    )
     assert hw_status == 0x0
 
     device_status = [
-        dword2int(await tb.read_csr(tb.reg_map.I3C_EC.SECFWRECOVERYIF.DEVICE_STATUS_0.base_addr, 4)),
-        dword2int(await tb.read_csr(tb.reg_map.I3C_EC.SECFWRECOVERYIF.DEVICE_STATUS_1.base_addr, 4)),
+        dword2int(
+            await tb.read_csr(tb.reg_map.I3C_EC.SECFWRECOVERYIF.DEVICE_STATUS_0.base_addr, 4)
+        ),
+        dword2int(
+            await tb.read_csr(tb.reg_map.I3C_EC.SECFWRECOVERYIF.DEVICE_STATUS_1.base_addr, 4)
+        ),
     ]
     assert device_status == [0x3, 0x0]  # DEVICE_STATUS_0 was earlier set to 0x3
 
@@ -326,9 +329,12 @@ async def test_payload_available(dut):
     # Initialize
     tb = await initialize(dut, timeout=50)
 
-    payload_size = dword2int(
-        await tb.read_csr(tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_STATUS_4.base_addr, 4)
-    ) * 4  # Multiply by 4 to get bytes from dwords
+    payload_size = (
+        dword2int(
+            await tb.read_csr(tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_STATUS_4.base_addr, 4)
+        )
+        * 4
+    )  # Multiply by 4 to get bytes from dwords
 
     payload_available = dut.xi3c_wrapper.recovery_payload_available_o
 
@@ -418,6 +424,86 @@ async def test_image_activated(dut):
     ), "Upon writing 0xFF to RECOVERY_CTRL byte 2 image_activated should be deasserted"
 
 
+@cocotb.test()
+async def test_i3c_bus_traffic_during_loopback(dut):
+    tb = await initialize(dut, timeout=500)
+
+    rtl_target_addr = 0x5A
+    sim_target_addr = 0x23  # Arbitrary
+
+    fbus = 12.5
+    i3c_controller = I3cController(
+        sda_i=dut.bus_sda,
+        sda_o=dut.sda_sim_ctrl_i,
+        scl_i=dut.bus_scl,
+        scl_o=dut.scl_sim_ctrl_i,
+        debug_state_o=None,
+        speed=fbus * 1e6,
+    )
+
+    i3c_target = I3CTarget(  # noqa
+        sda_i=dut.bus_sda,
+        sda_o=dut.sda_sim_target_i,
+        scl_i=dut.bus_scl,
+        scl_o=dut.scl_sim_target_i,
+        debug_state_o=None,
+        speed=fbus * 1e6,
+        address=sim_target_addr,
+    )
+
+    run_target_bus_traffic = Event()
+
+    async def target_bus_traffic(addr, run_condition):
+        await run_condition.wait()
+        while run_condition.is_set():
+            # Send data to simulated target
+            await i3c_controller.i3c_write(addr, [random.randint(0, 255)])
+
+    fifo_size = dword2int(
+        await tb.read_csr(tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_STATUS_4.base_addr, 4)
+    )
+
+    for addr in [sim_target_addr, rtl_target_addr]:
+        # Random delay to start transfer in the middle of I3C transaction
+
+        for _ in range(10):  # Arbitrary number of repetitions
+            payload_data = [random.randint(0, 2**32 - 1) for _ in range(fifo_size)]
+            delay_cycles = random.randint(0, 1000)
+            dut._log.info(f"Randomized delay is {delay_cycles} clock cycles")
+
+            # Start I3C traffic
+            bus_traffic = cocotb.start_soon(target_bus_traffic(addr, run_target_bus_traffic))
+            run_target_bus_traffic.set()
+
+            # Wait for random number of cycles and start write to Indirect FIFO via bypass
+            await ClockCycles(tb.clk, delay_cycles)
+            write_fifo = cocotb.start_soon(
+                write_to_indirect_fifo(tb, payload_data, format="dwords")
+            )
+
+            # Wait for random number of cycles and start read from Indirect FIFO via bypass
+            await ClockCycles(tb.clk, delay_cycles)
+            payload_received = []
+            for _ in range(fifo_size):
+                d = dword2int(
+                    await tb.read_csr(
+                        tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_DATA.base_addr, 4
+                    )
+                )
+                payload_received.append(d)
+
+            # Payload write/read to I3C Core finished so disable I3C bus traffic generator
+            await Join(write_fifo)
+            run_target_bus_traffic.clear()
+            await Join(bus_traffic)
+
+            dut._log.info("Received data: " + " ".join([hex(w) for w in payload_received]))
+            dut._log.info("Expected data: " + " ".join([hex(w) for w in payload_data]))
+            assert (
+                payload_data == payload_received
+            ), "Reiceved payload data does not match sent data!"
+
+
 @cocotb.test()
 async def test_recovery_flow(dut):
     """
@@ -479,7 +565,7 @@ async def mcu_agent():
         # Write image size to Indirect FIFO Control Image size field
         await tb.write_csr_field(
             tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_CTRL_1.base_addr,
-            tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_CTRL_1.IMAGE_SIZE_LSB,
+            tb.reg_map.I3C_EC.SECFWRECOVERYIF.INDIRECT_FIFO_CTRL_1.IMAGE_SIZE,
             image_size,
         )
         # Clear Indirect FIFO Reset