Resolve width errors

Internal-tag: [#74406]

Author: robertszczepanski

src/ctrl/descriptor_ibi.sv

@@ -94,7 +94,7 @@ module descriptor_ibi #(
       // -1 to compensate for comparison with data_cnt
       data_len   <= ibi_queue_rdata_i[7:0] - 1;
       // Divide by 4 and round up
-      data_words <= ibi_queue_rdata_i[7:2] + |ibi_queue_rdata_i[1:0];
+      data_words <= 8'(ibi_queue_rdata_i[7:2] + |ibi_queue_rdata_i[1:0]);
     end
 
   // Data counter

src/ctrl/descriptor_tx.sv

@@ -102,7 +102,7 @@ module descriptor_tx #(
   end
 
   assign data_len = tx_descriptor[15:0];
-  assign data_len_words = (data_len >> 2);
+  assign data_len_words = TtiTxDescDataWidth'(data_len >> 2);
   // Add 1 to depth, because there is one word in the Nto8 converter
   assign tx_start = ~tx_pending && descriptor_valid &&
                     ((tti_tx_queue_depth_i+1'b1) >= data_len_words);

src/ctrl/ibi.sv

@@ -201,7 +201,7 @@ module ibi (
       end
       SendTbit: begin
         bus_tx_req_bit_o   = 1'b1;
-        bus_tx_req_value_o = !ibi_byte_last_i;
+        bus_tx_req_value_o = 8'(!ibi_byte_last_i);
         bus_tx_sel_od_pp_o = 1'b1;
       end
       default: begin

src/ctrl/width_converter_Nto8.sv

@@ -50,7 +50,7 @@ module width_converter_Nto8 #(
     else begin
       if (source_flush_i) sreg <= '0;
       else if ((bcnt == '0) & sink_valid_i & sink_ready_o) sreg <= sink_data_i;
-      else if ((bcnt != '0) & source_valid_o & source_ready_i) sreg <= sreg >> 8;
+      else if ((bcnt != '0) & source_valid_o & source_ready_i) sreg <= Width'(sreg >> 8);
     end
 
   // Data output

src/recovery/recovery_executor.sv

@@ -217,7 +217,7 @@ module recovery_executor
   // ....................................................
 
   // Data counter
-  assign dcnt_next = (|cmd_len_i[1:0]) ? (cmd_len_i / 4 + 1) : (cmd_len_i / 4);  // Divide by 4, round up
+  assign dcnt_next = (|cmd_len_i[1:0]) ? 16'(cmd_len_i / 4 + 1) : 16'(cmd_len_i / 4);  // Divide by 4, round up
 
   always_ff @(posedge clk_i)
     unique case (state_q)