Improve TE support

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>

Author: mtdudek

src/ctrl/ccc.sv

@@ -96,6 +96,7 @@ module ccc
     input logic ccc_valid_i,
 
     output logic done_fsm_o,
+    output logic invalid_ccc_o,
     output logic next_ccc_o,
 
     // Bus Monitor interface
@@ -344,6 +345,9 @@ module ccc
 
   logic       get_status_in_progress;
 
+  logic       ccc_expected_parity;
+  assign ccc_expected_parity = ^{ccc_i, 1'b1};
+
   always_ff @(posedge clk_i or negedge rst_ni) begin : report_get_status_done
     if (~rst_ni) begin
       get_status_in_progress <= '0;
@@ -428,7 +432,8 @@ module ccc
     DoneCCC,
     HandleENTDAA,
     HandleTargetENTDAA,
-    HandleVirtualTargetENTDAA
+    HandleVirtualTargetENTDAA,
+    CCCError
   } state_e;
 
   state_e state_q, state_d;
@@ -468,6 +473,13 @@ module ccc
   logic is_byte_rsvd_addr;
   assign is_byte_rsvd_addr = (rx_data == {7'h7E, 1'b0}) | (command_addr == 7'h7E);
 
+  logic is_incorrect_byte_match;
+  assign is_incorrect_byte_match = (rx_data inside {
+        8'h7C, 8'hBC, 8'hDC, 8'hEC, 8'hF4, 8'hF8, 8'hFE, 8'hFD
+      }) | (command_addr inside {
+        8'h7C, 8'hBC, 8'hDC, 8'hEC, 8'hF4, 8'hF8, 8'hFE, 8'hFD
+      });
+
   logic is_byte_our_dynamic_addr;
   logic is_byte_our_virtual_dynamic_addr;
   logic is_byte_our_static_addr;
@@ -488,7 +500,6 @@ module ccc
   assign is_byte_virtual_addr = is_byte_our_virtual_dynamic_addr | is_byte_our_virtual_static_addr;
 
   logic supported_direct_command_code;
-
   assign supported_direct_command_code = command_code inside {
     // Setters
     `I3C_DIRECT_SETDASA,
@@ -509,8 +520,32 @@ module ccc
     `I3C_DIRECT_GETCAPS
   };
 
-  logic unsupported_def_byte;
+  logic read_only_command;
+  assign read_only_command = command_code inside {
+    `I3C_DIRECT_GETSTATUS,
+    `I3C_DIRECT_GETCAPS,
+    `I3C_DIRECT_GETBCR,
+    `I3C_DIRECT_GETDCR,
+    `I3C_DIRECT_GETMWL,
+    `I3C_DIRECT_GETMRL,
+    `I3C_DIRECT_GETPID
+  };
+
+  logic write_only_command;
+  assign write_only_command =  command_code inside {
+    `I3C_DIRECT_SETDASA,
+    `I3C_DIRECT_SETNEWDA,
+    `I3C_DIRECT_SETXTIME,
+    `I3C_DIRECT_SETMWL,
+    `I3C_DIRECT_SETMRL,
+    `I3C_DIRECT_ENEC,
+    `I3C_DIRECT_DISEC
+  };
+
+  logic direction_error;
+  assign direction_error = (read_only_command & ~command_rnw) | (write_only_command & command_rnw);
 
+  logic unsupported_def_byte;
   assign unsupported_def_byte = have_defining_byte & valid_defining_byte & (
         (command_code == `I3C_DIRECT_RSTACT) & ~(defining_byte inside {8'h00, 8'h01, 8'h02, 8'h81, 8'h82})
       | (command_code == `I3C_DIRECT_GETCAPS) & ~(defining_byte inside {8'h00, 8'h93}));
@@ -519,10 +554,11 @@ module ccc
   assign supported_direct_command = supported_direct_command_code & ~unsupported_def_byte;
 
   logic direct_addr_ack;
-
-  assign direct_addr_ack = (command_code == `I3C_DIRECT_SETDASA) ?
-      ((is_byte_our_static_addr && ~target_dyn_address_valid_i) | (is_byte_our_virtual_static_addr && ~virtual_target_dyn_address_valid_i)) :
-      ((is_byte_our_addr | is_byte_virtual_addr) & supported_direct_command  | is_byte_rsvd_addr );
+  assign direct_addr_ack = ~direction_error & ((command_code == `I3C_DIRECT_SETDASA) ?
+      ((is_byte_our_static_addr && ~target_dyn_address_valid_i) |
+        (is_byte_our_virtual_static_addr && ~virtual_target_dyn_address_valid_i)) :
+      ((is_byte_our_addr | is_byte_virtual_addr) & supported_direct_command |
+        is_byte_rsvd_addr ));
 
   always_ff @(posedge clk_i or negedge rst_ni) begin : proc_addr
     if (~rst_ni) begin
@@ -561,34 +597,36 @@ module ccc
       ent_hdr_6_o <= '0;
       ent_hdr_7_o <= '0;
     end else begin
-      unique case(command_code)
-        `I3C_BCAST_ENTHDR0:
-          ent_hdr_0_o <= '1;
-        `I3C_BCAST_ENTHDR1:
-          ent_hdr_1_o <= '1;
-        `I3C_BCAST_ENTHDR2:
-          ent_hdr_2_o <= '1;
-        `I3C_BCAST_ENTHDR3:
-          ent_hdr_3_o <= '1;
-        `I3C_BCAST_ENTHDR4:
-          ent_hdr_4_o <= '1;
-        `I3C_BCAST_ENTHDR5:
-          ent_hdr_5_o <= '1;
-        `I3C_BCAST_ENTHDR6:
-          ent_hdr_6_o <= '1;
-        `I3C_BCAST_ENTHDR7:
-          ent_hdr_7_o <= '1;
-        default: begin
-          ent_hdr_0_o <= '0;
-          ent_hdr_1_o <= '0;
-          ent_hdr_2_o <= '0;
-          ent_hdr_3_o <= '0;
-          ent_hdr_4_o <= '0;
-          ent_hdr_5_o <= '0;
-          ent_hdr_6_o <= '0;
-          ent_hdr_7_o <= '0;
-        end
-      endcase
+      if (bus_tx_done_i & (state_q == RxTbit) & (ccc_expected_parity == bus_rx_data_i[0])) begin
+        unique case(command_code)
+            `I3C_BCAST_ENTHDR0:
+              ent_hdr_0_o <= '1;
+            `I3C_BCAST_ENTHDR1:
+              ent_hdr_1_o <= '1;
+            `I3C_BCAST_ENTHDR2:
+              ent_hdr_2_o <= '1;
+            `I3C_BCAST_ENTHDR3:
+              ent_hdr_3_o <= '1;
+            `I3C_BCAST_ENTHDR4:
+              ent_hdr_4_o <= '1;
+            `I3C_BCAST_ENTHDR5:
+              ent_hdr_5_o <= '1;
+            `I3C_BCAST_ENTHDR6:
+              ent_hdr_6_o <= '1;
+            `I3C_BCAST_ENTHDR7:
+              ent_hdr_7_o <= '1;
+            default: begin
+              ent_hdr_0_o <= '0;
+              ent_hdr_1_o <= '0;
+              ent_hdr_2_o <= '0;
+              ent_hdr_3_o <= '0;
+              ent_hdr_4_o <= '0;
+              ent_hdr_5_o <= '0;
+              ent_hdr_6_o <= '0;
+              ent_hdr_7_o <= '0;
+            end
+        endcase
+      end
     end
   end
 
@@ -606,8 +644,11 @@ module ccc
       end
       RxTbit: begin
         if (bus_rx_done_i) begin
+          // Check T-bit
+          if (ccc_expected_parity != bus_rx_data_i[0]) begin
+            state_d = CCCError;
           // have defining byte
-          if (have_defining_byte && command_code == `I3C_DIRECT_GETCAPS) state_d = RxDefByteOrBusCond;
+          end else if (have_defining_byte && command_code == `I3C_DIRECT_GETCAPS) state_d = RxDefByteOrBusCond;
           else if (have_defining_byte) state_d = RxDefByte;
           else begin
             // ENTDAA is special
@@ -690,9 +731,10 @@ module ccc
             else state_d = WaitForBusCond;
           end
           else begin
-            if (is_byte_rsvd_addr) state_d = NextCCC;
-            else if ((is_byte_our_addr || is_byte_virtual_addr) && command_rnw && supported_direct_command) state_d = TxData;
-            else if ((is_byte_our_addr || is_byte_virtual_addr) && ~command_rnw && supported_direct_command) begin
+            if (is_incorrect_byte_match) state_d = CCCError;
+            else if (is_byte_rsvd_addr) state_d = NextCCC;
+            else if ((is_byte_our_addr || is_byte_virtual_addr) && command_rnw && supported_direct_command && ~direction_error) state_d = TxData;
+            else if ((is_byte_our_addr || is_byte_virtual_addr) && ~command_rnw && supported_direct_command && ~direction_error) begin
               if (command_code == `I3C_DIRECT_SETXTIME) state_d = RxSubCmdByte;
               else state_d = RxData;
             end else state_d = WaitForBusCond;
@@ -731,6 +773,9 @@ module ccc
       DoneCCC: begin
         state_d = Idle;
       end
+      CCCError: begin
+        state_d = Idle;
+      end
       default: begin
       end
     endcase
@@ -748,6 +793,7 @@ module ccc
 
     done_fsm_o = '0;
     next_ccc_o = '0;
+    invalid_ccc_o = '0;
     unique case (state_q)
       Idle: begin
 
@@ -819,6 +865,10 @@ module ccc
       DoneCCC: begin
         done_fsm_o = '1;
       end
+      CCCError: begin
+        invalid_ccc_o = '1;
+        done_fsm_o = '1;
+      end
       default: begin
       end
     endcase

src/ctrl/controller_standby_i3c.sv

@@ -240,6 +240,7 @@ module controller_standby_i3c
   logic target_reset_detect;
   logic hdr_exit_detect;
   logic is_in_hdr_mode;
+  logic te0_detected;
 
   // SubFSMs status
   logic ibi_pending;
@@ -249,6 +250,7 @@ module controller_standby_i3c
   logic [7:0] ccc;
   logic ccc_valid;
   logic is_ccc_done;
+  logic invalid_ccc;
   logic is_next_ccc;
   logic is_hotjoin_done;
 
@@ -447,13 +449,15 @@ module controller_standby_i3c
       .target_reset_detect_i      (target_reset_detect),
       .hdr_exit_detect_i          (hdr_exit_detect),
       .is_in_hdr_mode_i           (is_in_hdr_mode),
+      .te0_detected_o             (te0_detected),
       .ibi_enable_i               (ibi_enable_i),
       .ibi_pending_i              (ibi_pending),
       .ibi_begin_o                (ibi_begin),
       .ibi_done_i                 (ibi_done),
       .ccc_o                      (ccc),
       .ccc_valid_o                (ccc_valid),
       .is_ccc_done_i              (is_ccc_done),
+      .invalid_ccc_i             (invalid_ccc),
       .is_next_ccc_i              (is_next_ccc),
       .is_hotjoin_done_i          (is_hotjoin_done),
       .last_addr_o                (bus_addr_o),
@@ -463,6 +467,7 @@ module controller_standby_i3c
       .sda_negedge_i              (ctrl_bus_i.sda.neg_edge),
       .sda_posedge_i              (ctrl_bus_i.sda.pos_edge),
       .bus_free_i                 (bus_free),
+      .bus_idle_i                 (bus_idle),
       .parity_err_o,
       .rx_overflow_err_o          (rx_overflow_err),
       .virtual_device_sel_o       (virtual_device_sel_o),
@@ -476,6 +481,7 @@ module controller_standby_i3c
       .ccc_i                     (ccc),
       .ccc_valid_i               (ccc_valid),
       .done_fsm_o                (is_ccc_done),
+      .invalid_ccc_o             (invalid_ccc),
       .next_ccc_o                (is_next_ccc),
       .bus_start_det_i           (ctrl_bus_i.start_det),
       .bus_rstart_det_i          (ctrl_bus_i.rstart_det),
@@ -637,12 +643,15 @@ module controller_standby_i3c
       .rx_idle_o        (bus_rx_idle)
   );
 
+  logic hdr_exit_trigger;
+  assign hdr_exit_trigger = is_in_hdr_mode | te0_detected;
+
   i3c_bus_monitor xbus_monitor (
       .clk_i,
       .rst_ni,
       .enable_i             (i3c_standby_en),
       .bus_i                (ctrl_bus_i),
-      .is_in_hdr_mode_i     (is_in_hdr_mode),
+      .is_in_hdr_mode_i     (hdr_exit_trigger),
       .hdr_exit_detect_o    (hdr_exit_detect),
       .target_reset_detect_o(target_reset_detect)
   );