@@ -91,7 +91,6 @@ module ccc
91
91
input logic rst_ni, // Async reset, active low
92
92
input logic [47 : 0 ] id_i,
93
93
94
- input logic arbitration_lost_i,
95
94
// CC is decoded from the frame by the primary FSM
96
95
input logic [7 : 0 ] ccc_i,
97
96
// Assert valid when you want to give control to this FSM
@@ -339,13 +338,13 @@ module ccc
339
338
// Mux TX access between regular CCC and ENTDAA
340
339
logic entdaa_tx_req_bit;
341
340
logic entdaa_tx_req_byte;
342
- logic entdaa_tx_req_value;
341
+ logic [ 7 : 0 ] entdaa_tx_req_value;
343
342
logic entdaa_tx_sel_od_pp;
344
343
logic entdaa_rx_req_bit;
345
344
logic entdaa_rx_req_byte;
346
345
logic ccc_tx_req_bit;
347
346
logic ccc_tx_req_byte;
348
- logic ccc_tx_req_value;
347
+ logic [ 7 : 0 ] ccc_tx_req_value;
349
348
logic ccc_tx_sel_od_pp;
350
349
logic ccc_rx_req_bit;
351
350
logic ccc_rx_req_byte;
@@ -967,7 +966,6 @@ module ccc
967
966
assign entas1_o = '0 ;
968
967
assign entas2_o = '0 ;
969
968
assign entas3_o = '0 ;
970
- assign entdaa_o = '0 ;
971
969
assign ent_tm_o = '0 ;
972
970
assign tm_o = '0 ;
973
971
assign ent_hdr_0_o = '0 ;
@@ -985,7 +983,7 @@ module ccc
985
983
.rst_ni, // Async reset, active low
986
984
.id_i,
987
985
988
- .start_daa_i (entdaa_start ),
986
+ .start_daa_i (entdaa_o ),
989
987
.done_daa_o (entdaa_done),
990
988
991
989
// Bus RX interface
@@ -995,7 +993,7 @@ module ccc
995
993
.bus_rx_req_byte_o (entdaa_rx_req_byte),
996
994
997
995
// Bus TX interface
998
- .bus_tx_done_i,
996
+ .bus_tx_done_i (bus_tx_done_i) ,
999
997
.bus_tx_req_byte_o (entdaa_tx_req_byte),
1000
998
.bus_tx_req_bit_o (entdaa_tx_req_bit),
1001
999
.bus_tx_req_value_o (entdaa_tx_req_value),
0 commit comments