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lines changed- .github/workflows/rtlmeter-pr-results.yml+1-1
- .github/workflows/rtlmeter.yml+2-2
- Changes+7-3
- ci/ci-script.bash+1
- docs/guide/connecting.rst+4-4
- docs/guide/exe_verilator.rst+7-8
- docs/guide/extensions.rst+9-6
- include/verilatedos.h+5
- src/V3Active.cpp-3
- src/V3ActiveTop.cpp-3
- src/V3AssertPre.cpp+17-3
- src/V3AstNodeOther.h+20
- src/V3AstNodeStmt.h-17
- src/V3AstNodes.cpp+9
- src/V3Broken.cpp+17-6
- src/V3Control.cpp+22-33
- src/V3EmitCFunc.h-1
- src/V3EmitV.cpp-12
- src/V3Error.cpp+7-4
- src/V3Error.h+2
- src/V3Force.cpp-1
- src/V3FuncOpt.cpp+1-2
- src/V3Gate.cpp-1
- src/V3LinkDot.cpp+30-9
- src/V3LinkParse.cpp-16
- src/V3Number.h+5
- src/V3OrderGraphBuilder.cpp-3
- src/V3Param.cpp+36-19
- src/V3Randomize.cpp+14-15
- src/V3SchedPartition.cpp-1
- src/V3Scope.cpp-9
- src/V3SplitVar.cpp-10
- src/V3Tristate.cpp+2
- src/V3Unknown.cpp+4-1
- src/V3Width.cpp+144-143
- src/verilog.y+14-19
- test_regress/driver.py+2-2
- test_regress/t/t_assert_always_unsup.py+2
- test_regress/t/t_assert_elab.v+5-1
- test_regress/t/t_class_param_circ_bad.out+1-2
- test_regress/t/t_debug_emitv.out-1
- test_regress/t/t_dist_warn_coverage.py-3
- test_regress/t/t_dpi_var.v+3-3
- test_regress/t/t_dpi_var.vlt+2-2
- test_regress/t/t_mod_interface_clocking.py+18
- test_regress/t/t_mod_interface_clocking.v+51
- test_regress/t/t_mod_interface_clocking_bad.out+7-1
- test_regress/t/t_mod_interface_clocking_bad.v+1-1
- test_regress/t/t_randomize.v+4
- test_regress/t/t_real_out_of_bounds.py+18
- test_regress/t/t_real_out_of_bounds.v+35
- test_regress/t/t_tri_inout_pins_inout.py+2-2
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