Merge pull request chipsalliance#341 from antmicro/packed_range_custom_wire

Packed range custom wire

Author: kamilrakoczy

uhdm-tests/opentitan/0001-Add-opentitan-patch-for-uhdm.patch

@@ -449,40 +449,6 @@ index 5324b4978..a1a858232 100644
    } reg2hw_wrap_t;
 
  endpackage : alert_pkg
-diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
-index 6b573e1b7..6a4f5b30e 100644
---- a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
-+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
-@@ -309,20 +309,20 @@ module flash_ctrl import flash_ctrl_pkg::*; (
-   end
- 
-   // extra region is the default region
--  flash_ctrl_reg2hw_mp_region_cfg_mreg_t [MpRegions:0] region_cfgs;
-+  logic [MpRegions*24:0] region_cfgs;
- 
--  assign region_cfgs[MpRegions-1:0] = reg2hw.mp_region_cfg[MpRegions-1:0];
-+  assign region_cfgs[(MpRegions - 1)*24-1:0] = reg2hw.mp_region_cfg[MpRegions*24-1:0];
- 
-   //default region
--  assign region_cfgs[MpRegions].base.q = '0;
--  assign region_cfgs[MpRegions].size.q = NumBanks * PagesPerBank;
--  assign region_cfgs[MpRegions].en.q = 1'b1;
--  assign region_cfgs[MpRegions].rd_en.q = reg2hw.default_region.rd_en.q;
--  assign region_cfgs[MpRegions].prog_en.q = reg2hw.default_region.prog_en.q;
--  assign region_cfgs[MpRegions].erase_en.q = reg2hw.default_region.erase_en.q;
-+  assign region_cfgs[(MpRegions - 1)*24+19:(MpRegions - 1)*24+11] = '0;
-+  assign region_cfgs[(MpRegions - 1)*24+10:(MpRegions - 1)*24+1] = NumBanks * PagesPerBank;
-+  assign region_cfgs[(MpRegions - 1)*24+23] = 1'b1;
-+  assign region_cfgs[(MpRegions - 1)*24+22] = reg2hw.default_region.rd_en.q;
-+  assign region_cfgs[(MpRegions - 1)*24+21] = reg2hw.default_region.prog_en.q;
-+  assign region_cfgs[(MpRegions - 1)*24+20] = reg2hw.default_region.erase_en.q;
-   // we are allowed to set default accessibility of data partitions
-   // however info partitions default to inaccessible
--  assign region_cfgs[MpRegions].partition.q = FlashPartData;
-+  assign region_cfgs[(MpRegions - 1)*24+0] = FlashPartData;
- 
-   flash_part_e flash_part_sel;
-   assign flash_part_sel = flash_part_e'(reg2hw.control.partition_sel.q);
 diff --git a/hw/ip/padctrl/rtl/padring.sv b/hw/ip/padctrl/rtl/padring.sv
 index fc8b3d183..2b94b0d67 100644
 --- a/hw/ip/padctrl/rtl/padring.sv
@@ -556,115 +522,6 @@ index 962d3b559..9d5a10c8c 100644
  `endif
    end
 
-diff --git a/hw/ip/rv_timer/rtl/rv_timer.sv b/hw/ip/rv_timer/rtl/rv_timer.sv
-index 9b939eedd..a4c91c238 100644
---- a/hw/ip/rv_timer/rtl/rv_timer.sv
-+++ b/hw/ip/rv_timer/rtl/rv_timer.sv
-@@ -31,10 +31,10 @@ module rv_timer (
- 
-   logic [N_HARTS-1:0] tick;
- 
--  logic [63:0] mtime_d  [N_HARTS];
--  logic [63:0] mtime    [N_HARTS];
--  logic [63:0] mtimecmp [N_HARTS][N_TIMERS]; // Only [harts][0] is connected to mtimecmp CSRs
--  logic        mtimecmp_update [N_HARTS][N_TIMERS];
-+  logic [63:0] mtime_d  ;
-+  logic [63:0] mtime    ;
-+  logic [63:0] mtimecmp; // Only [harts][0] is connected to mtimecmp CSRs
-+  logic        mtimecmp_update;
- 
-   logic [N_HARTS*N_TIMERS-1:0] intr_timer_set;
-   logic [N_HARTS*N_TIMERS-1:0] intr_timer_en;
-@@ -52,25 +52,25 @@ module rv_timer (
- 
-   // Once reggen supports nested multireg, the following can be automated. For the moment, it must
-   // be connected manually.
--  assign active[0]  = reg2hw.ctrl[0].q;
-+  assign active[0]  = reg2hw.ctrl.q;
-   assign prescaler = '{reg2hw.cfg0.prescale.q};
-   assign step      = '{reg2hw.cfg0.step.q};
- 
-   assign hw2reg.timer_v_upper0.de = tick[0];
-   assign hw2reg.timer_v_lower0.de = tick[0];
--  assign hw2reg.timer_v_upper0.d = mtime_d[0][63:32];
--  assign hw2reg.timer_v_lower0.d = mtime_d[0][31: 0];
--  assign mtime[0] = {reg2hw.timer_v_upper0.q, reg2hw.timer_v_lower0.q};
-+  assign hw2reg.timer_v_upper0.d = mtime_d[63:32];
-+  assign hw2reg.timer_v_lower0.d = mtime_d[31: 0];
-+  assign mtime = {reg2hw.timer_v_upper0.q, reg2hw.timer_v_lower0.q};
-   assign mtimecmp = '{'{{reg2hw.compare_upper0_0.q,reg2hw.compare_lower0_0.q}}};
--  assign mtimecmp_update[0][0] = reg2hw.compare_upper0_0.qe | reg2hw.compare_lower0_0.qe;
-+  assign mtimecmp_update = reg2hw.compare_upper0_0.qe | reg2hw.compare_lower0_0.qe;
- 
-   assign intr_timer_expired_0_0_o = intr_out[0];
--  assign intr_timer_en            = reg2hw.intr_enable0[0].q;
--  assign intr_timer_state_q       = reg2hw.intr_state0[0].q;
--  assign intr_timer_test_q        = reg2hw.intr_test0[0].q;
--  assign intr_timer_test_qe       = reg2hw.intr_test0[0].qe;
--  assign hw2reg.intr_state0[0].de = intr_timer_state_de | mtimecmp_update[0][0];
--  assign hw2reg.intr_state0[0].d  = intr_timer_state_d & ~mtimecmp_update[0][0];
-+  assign intr_timer_en            = reg2hw.intr_enable0.q;
-+  assign intr_timer_state_q       = reg2hw.intr_state0.q;
-+  assign intr_timer_test_q        = reg2hw.intr_test0.q;
-+  assign intr_timer_test_qe       = reg2hw.intr_test0.qe;
-+  assign hw2reg.intr_state0.de = intr_timer_state_de | mtimecmp_update;
-+  assign hw2reg.intr_state0.d  = intr_timer_state_d & ~mtimecmp_update;
- 
- 
-   for (genvar h = 0 ; h < N_HARTS ; h++) begin : gen_harts
-@@ -96,14 +96,14 @@ module rv_timer (
-       .rst_ni,
- 
-       .active    (active[h]),
--      .prescaler (prescaler[h]),
--      .step      (step[h]),
-+      .prescaler (prescaler),
-+      .step      (step),
- 
-       .tick      (tick[h]),
- 
--      .mtime_d   (mtime_d[h]),
--      .mtime     (mtime[h]),
--      .mtimecmp  (mtimecmp[h]),
-+      .mtime_d   (mtime_d),
-+      .mtime     (mtime),
-+      .mtimecmp  (mtimecmp),
- 
-       .intr      (intr_timer_set[h*N_TIMERS+:N_TIMERS])
-     );
-diff --git a/hw/ip/rv_timer/rtl/rv_timer_reg_pkg.sv b/hw/ip/rv_timer/rtl/rv_timer_reg_pkg.sv
-index 2addad698..37e6d79c4 100644
---- a/hw/ip/rv_timer/rtl/rv_timer_reg_pkg.sv
-+++ b/hw/ip/rv_timer/rtl/rv_timer_reg_pkg.sv
-@@ -78,15 +78,15 @@ package rv_timer_reg_pkg;
-   // Register to internal design logic //
-   ///////////////////////////////////////
-   typedef struct packed {
--    rv_timer_reg2hw_ctrl_mreg_t [0:0] ctrl; // [154:154]
-+    rv_timer_reg2hw_ctrl_mreg_t ctrl; // [154:154]
-     rv_timer_reg2hw_cfg0_reg_t cfg0; // [153:134]
-     rv_timer_reg2hw_timer_v_lower0_reg_t timer_v_lower0; // [133:102]
-     rv_timer_reg2hw_timer_v_upper0_reg_t timer_v_upper0; // [101:70]
-     rv_timer_reg2hw_compare_lower0_0_reg_t compare_lower0_0; // [69:37]
-     rv_timer_reg2hw_compare_upper0_0_reg_t compare_upper0_0; // [36:4]
--    rv_timer_reg2hw_intr_enable0_mreg_t [0:0] intr_enable0; // [3:3]
--    rv_timer_reg2hw_intr_state0_mreg_t [0:0] intr_state0; // [2:2]
--    rv_timer_reg2hw_intr_test0_mreg_t [0:0] intr_test0; // [1:0]
-+    rv_timer_reg2hw_intr_enable0_mreg_t intr_enable0; // [3:3]
-+    rv_timer_reg2hw_intr_state0_mreg_t intr_state0; // [2:2]
-+    rv_timer_reg2hw_intr_test0_mreg_t intr_test0; // [1:0]
-   } rv_timer_reg2hw_t;
- 
-   ///////////////////////////////////////
-@@ -95,7 +95,7 @@ package rv_timer_reg_pkg;
-   typedef struct packed {
-     rv_timer_hw2reg_timer_v_lower0_reg_t timer_v_lower0; // [67:36]
-     rv_timer_hw2reg_timer_v_upper0_reg_t timer_v_upper0; // [35:4]
--    rv_timer_hw2reg_intr_state0_mreg_t [0:0] intr_state0; // [3:2]
-+    rv_timer_hw2reg_intr_state0_mreg_t intr_state0; // [3:2]
-   } rv_timer_hw2reg_t;
- 
-   // Register Address
 diff --git a/hw/ip/tlul/rtl/tlul_adapter_sram.sv b/hw/ip/tlul/rtl/tlul_adapter_sram.sv
 index 6e2f33191..2820baadd 100644
 --- a/hw/ip/tlul/rtl/tlul_adapter_sram.sv