Update patch

Signed-off-by: Kamil Rakoczy <[email protected]>

Author: kamilrakoczy

uhdm-tests/opentitan/0001-Add-opentitan-patch-for-uhdm.patch

@@ -522,122 +522,6 @@ index 962d3b559..9d5a10c8c 100644
  `endif
    end
 
-diff --git a/hw/ip/tlul/rtl/tlul_adapter_sram.sv b/hw/ip/tlul/rtl/tlul_adapter_sram.sv
-index 6e2f33191..2820baadd 100644
---- a/hw/ip/tlul/rtl/tlul_adapter_sram.sv
-+++ b/hw/ip/tlul/rtl/tlul_adapter_sram.sv
-@@ -134,20 +134,17 @@ module tlul_adapter_sram #(
-     end
-   end
- 
--  assign tl_o = '{
--      d_valid  : d_valid ,
--      d_opcode : (d_valid && reqfifo_rdata.op != OpRead) ? AccessAck : AccessAckData,
--      d_param  : '0,
--      d_size   : (d_valid) ? reqfifo_rdata.size : '0,
--      d_source : (d_valid) ? reqfifo_rdata.source : '0,
--      d_sink   : 1'b0,
--      d_data   : (d_valid && rspfifo_rvalid && reqfifo_rdata.op == OpRead)
--                 ? rspfifo_rdata.data : '0,
--      d_user   : '0,
--      d_error  : d_valid && d_error,
--
--      a_ready  : (gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready
--  };
-+  assign tl_o.d_valid   = d_valid;
-+  assign tl_o.d_opcode  = (d_valid && reqfifo_rdata.op != OpRead) ? AccessAck : AccessAckData;
-+  assign tl_o.d_param   = '0;
-+  assign tl_o.d_size    = (d_valid) ? reqfifo_rdata.size : '0;
-+  assign tl_o.d_source  = (d_valid) ? reqfifo_rdata.source : '0;
-+  assign tl_o.d_sink    = 1'b0;
-+  assign tl_o.d_data    = (d_valid && rspfifo_rvalid && reqfifo_rdata.op == OpRead) ? rspfifo_rdata.data : '0;
-+  assign tl_o.d_user    = '0;
-+  assign tl_o.d_error   = d_valid && d_error;
-+
-+  assign tl_o.a_ready   = (gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready;
- 
-   // a_ready depends on the FIFO full condition and grant from SRAM (or SRAM arbiter)
-   // assemble response, including read response, write response, and error for unsupported stuff
-@@ -171,8 +168,8 @@ module tlul_adapter_sram #(
-   end
- 
-   // Convert byte mask to SRAM bit mask for writes, and only forward valid data
--  logic [WidthMult-1:0][top_pkg::TL_DW-1:0] wmask_int;
--  logic [WidthMult-1:0][top_pkg::TL_DW-1:0] wdata_int;
-+  logic [(WidthMult * top_pkg::TL_DW) - 1:0] wmask_int;
-+  logic [(WidthMult * top_pkg::TL_DW) - 1:0] wdata_int;
- 
-   always_comb begin
-     wmask_int = '0;
-@@ -180,8 +177,8 @@ module tlul_adapter_sram #(
- 
-     if (tl_i.a_valid) begin
-       for (int i = 0 ; i < top_pkg::TL_DW/8 ; i++) begin
--        wmask_int[woffset][8*i +: 8] = {8{tl_i.a_mask[i]}};
--        wdata_int[woffset][8*i +: 8] = (tl_i.a_mask[i] && we_o) ? tl_i.a_data[8*i+:8] : '0;
-+        wmask_int[(woffset * top_pkg::TL_DW) + (8 * i) +: 8] = {8{tl_i.a_mask[i]}};
-+        wdata_int[(woffset * top_pkg::TL_DW) + (8 * i) +: 8] = (tl_i.a_mask[i] && we_o) ? tl_i.a_data[8*i+:8] : '0;
-       end
-     end
-   end
-@@ -221,19 +218,15 @@ module tlul_adapter_sram #(
-   // End: Request Error Detection
- 
-   assign reqfifo_wvalid = a_ack ; // Push to FIFO only when granted
--  assign reqfifo_wdata  = '{
--    op:     (tl_i.a_opcode != Get) ? OpWrite : OpRead, // To return AccessAck for opcode error
--    error:  error_internal,
--    size:   tl_i.a_size,
--    source: tl_i.a_source
--  }; // Store the request only. Doesn't have to store data
-+  assign reqfifo_wdata.op      = (tl_i.a_opcode != Get) ? OpWrite : OpRead; // To return AccessAck for opcode error
-+  assign reqfifo_wdata.error   = error_internal;
-+  assign reqfifo_wdata.size    = tl_i.a_size;
-+  assign reqfifo_wdata.source  = tl_i.a_source;
-   assign reqfifo_rready = d_ack ;
- 
-   // push together with ReqFIFO, pop upon returning read
--  assign sramreqfifo_wdata = '{
--    mask    : tl_i.a_mask,
--    woffset : woffset
--  };
-+  assign sramreqfifo_wdata.mask     = tl_i.a_mask;
-+  assign sramreqfifo_wdata.woffset  = woffset;
-   assign sramreqfifo_wvalid = sram_ack & ~we_o;
-   assign sramreqfifo_rready = rspfifo_wvalid;
- 
-@@ -241,26 +234,23 @@ module tlul_adapter_sram #(
- 
-   // Make sure only requested bytes are forwarded
-   logic [SramDw-1:0] rdata;
--  logic [WidthMult-1:0][top_pkg::TL_DW-1:0] rmask;
-+  logic [(WidthMult * top_pkg::TL_DW) - 1:0] rmask;
-   //logic [SramDw-1:0] rmask;
-   logic [top_pkg::TL_DW-1:0] rdata_tlword;
- 
-   always_comb begin
-     rmask = '0;
-     for (int i = 0 ; i < top_pkg::TL_DW/8 ; i++) begin
--      rmask[sramreqfifo_rdata.woffset][8*i +: 8] = {8{sramreqfifo_rdata.mask[i]}};
-+      rmask[(sramreqfifo_rdata.woffset * top_pkg::TL_DW) + (8 * i) +: 8] = {8{sramreqfifo_rdata.mask[i]}};
-     end
-   end
- 
-   assign rdata = rdata_i & rmask;
-   assign rdata_tlword = rdata[sramreqfifo_rdata.woffset * top_pkg::TL_DW +: top_pkg::TL_DW];
- 
--  assign rspfifo_wdata  = '{
--    data : rdata_tlword,
--    error: rerror_i[1] // Only care for Uncorrectable error
--  };
--  assign rspfifo_rready = (reqfifo_rdata.op == OpRead & ~reqfifo_rdata.error)
--                        ? reqfifo_rready : 1'b0 ;
-+  assign rspfifo_wdata.data   = rdata_tlword;
-+  assign rspfifo_wdata.error  = rerror_i[1]; // Only care for Uncorrectable error
-+  assign rspfifo_rready = (reqfifo_rdata.op == OpRead & ~reqfifo_rdata.error) ? reqfifo_rready : 1'b0 ;
- 
-   // FIFO instance: REQ, RSP
- 
 diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
 index 2acc14e86..c6aa89066 100644
 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv