Bump ibex

Signed-off-by: Kamil Rakoczy <[email protected]>

Author: kamilrakoczy

uhdm-tests/ibex/ibex

@@ -1,101 +1,8 @@
-From e9601e43c6a07014a29f90d9f747f4abe0f1fb9b Mon Sep 17 00:00:00 2001
-From: Kamil Rakoczy <[email protected]>
-Date: Thu, 23 Dec 2021 12:57:35 +0100
-Subject: [PATCH 2/3] add synth surelog target
-
-Signed-off-by: Kamil Rakoczy <[email protected]>
----
- examples/fpga/artya7/top_artya7.core | 25 ++++++++++++++++++++++---
- 1 file changed, 22 insertions(+), 3 deletions(-)
-
-diff --git a/examples/fpga/artya7/top_artya7.core b/examples/fpga/artya7/top_artya7.core
-index 4493a8ae..9a5e538b 100644
---- a/examples/fpga/artya7/top_artya7.core
-+++ b/examples/fpga/artya7/top_artya7.core
-@@ -2,7 +2,7 @@ CAPI=2:
- # Copyright lowRISC contributors.
- # Licensed under the Apache License, Version 2.0, see LICENSE for details.
- # SPDX-License-Identifier: Apache-2.0
--name: "lowrisc:ibex:top_artya7:0.1"
-+name: "lowrisc:ibex:top_artya7_surelog:0.1"
- description: "Ibex example toplevel for Arty A7 boards (both, -35 and -100)"
- filesets:
-   files_rtl_artya7:
-@@ -17,6 +17,10 @@ filesets:
-     files:
-       - data/pins_artya7.xdc
-     file_type: xdc
-+  files_constraints_sdc:
-+    files:
-+      - data/pins_artya7.sdc
-+    file_type: SDC
- 
-   files_tcl:
-     files:
-@@ -41,7 +45,7 @@ parameters:
-     datatype: str
-     paramtype: vlogdefine
-     description: Primitives implementation to use, e.g. "prim_pkg::ImplGeneric".
-- 
-+
-   FPGAPowerAnalysis:
-     datatype: int
-     paramtype: vlogparam
-@@ -53,7 +57,7 @@ targets:
-     filesets:
-       - files_rtl_artya7
-       - files_constraints
--      - files_tcl
-+      - tool_symbiflow ? (files_constraints_sdc)
-     toplevel: top_artya7
-     parameters:
-       - SRAMInitFile
-@@ -62,3 +66,18 @@ targets:
-     tools:
-       vivado:
-         part: "xc7a100tcsg324-1"  # Default to Arty A7-100
-+        synth: "yosys"
-+        yosys_synth_options: ['-iopad', '-family xc7', '-run :check', "frontend=surelog"]
-+        yosys_read_options: ['-noassert', '-debug']
-+        surelog_options: ['--disable-feature=parametersubstitution', '-DSYNTHESIS']
-+      yosys:
-+        arch: "xilinx"
-+        yosys_synth_options: ['-iopad', '-family xc7', '-run :check', "frontend=surelog"]
-+        yosys_read_options: ['-noassert']
-+        surelog_options: ['--disable-feature=parametersubstitution', '-DSYNTHESIS']
-+      symbiflow:
-+        package: "csg324-1"
-+        part: "xc7a35t"
-+        pnr: "vtr"
-+        vendor: "xilinx"
-+        surelog_options: ['--disable-feature=parametersubstitution', '-DSYNTHESIS']
--- 
-2.33.1
-
-From 7b0e214fcb86aac8331da89f378ba0dbccc4f0d3 Mon Sep 17 00:00:00 2001
-From: Kamil Rakoczy <[email protected]>
-Date: Thu, 23 Dec 2021 12:58:11 +0100
-Subject: [PATCH 3/3] ibex: change ram_2p to ram_1p
-
----
- examples/fpga/artya7/rtl/top_artya7.sv | 46 +++++++++++++++-----------
- shared/fpga_xilinx.core                |  4 +--
- 2 files changed, 28 insertions(+), 22 deletions(-)
-
 diff --git a/examples/fpga/artya7/rtl/top_artya7.sv b/examples/fpga/artya7/rtl/top_artya7.sv
-index 5efbf270..e91db9fd 100644
+index b15ee978..7ed562bb 100644
 --- a/examples/fpga/artya7/rtl/top_artya7.sv
 +++ b/examples/fpga/artya7/rtl/top_artya7.sv
-@@ -8,7 +8,7 @@ module top_artya7 (
-     output [3:0]        LED
- );
- 
--  parameter int          MEM_SIZE     = 256 * 1024; // 256 kB
-+  parameter int          MEM_SIZE     = 32 * 1024; // 32 kB
-   parameter logic [31:0] MEM_START    = 32'h00000000;
-   parameter logic [31:0] MEM_MASK     = MEM_SIZE-1;
-   parameter              SRAMInitFile = "";
-@@ -84,28 +84,34 @@ module top_artya7 (
+@@ -87,28 +87,34 @@ module top_artya7 (
    );
 
    // SRAM block for instruction and data storage
@@ -148,7 +55,59 @@ index 5efbf270..e91db9fd 100644
 +    .rdata_o   ( instr_rdata    )
    );
 
+   assign instr_gnt = instr_req;
+diff --git a/examples/fpga/artya7/top_artya7.core b/examples/fpga/artya7/top_artya7.core
+index 4493a8ae..bbe9c6c8 100644
+--- a/examples/fpga/artya7/top_artya7.core
++++ b/examples/fpga/artya7/top_artya7.core
+@@ -2,7 +2,7 @@ CAPI=2:
+ # Copyright lowRISC contributors.
+ # Licensed under the Apache License, Version 2.0, see LICENSE for details.
+ # SPDX-License-Identifier: Apache-2.0
+-name: "lowrisc:ibex:top_artya7:0.1"
++name: "lowrisc:ibex:top_artya7_surelog:0.1"
+ description: "Ibex example toplevel for Arty A7 boards (both, -35 and -100)"
+ filesets:
+   files_rtl_artya7:
+@@ -17,6 +17,10 @@ filesets:
+     files:
+       - data/pins_artya7.xdc
+     file_type: xdc
++  files_constraints_sdc:
++    files:
++      - data/pins_artya7.sdc
++    file_type: SDC
 
+   files_tcl:
+     files:
+@@ -53,7 +57,7 @@ targets:
+     filesets:
+       - files_rtl_artya7
+       - files_constraints
+-      - files_tcl
++      - tool_symbiflow ? (files_constraints_sdc)
+     toplevel: top_artya7
+     parameters:
+       - SRAMInitFile
+@@ -62,3 +66,18 @@ targets:
+     tools:
+       vivado:
+         part: "xc7a100tcsg324-1"  # Default to Arty A7-100
++        synth: "yosys"
++        yosys_synth_options: ['-iopad', '-family xc7', '-run :check', "frontend=surelog"]
++        yosys_read_options: ['-debug']
++        surelog_options: ['--disable-feature=parametersubstitution', '-DSYNTHESIS']
++      yosys:
++        arch: "xilinx"
++        yosys_synth_options: ['-iopad', '-family xc7', '-run :check', "frontend=surelog"]
++        yosys_read_options: ['-debug']
++        surelog_options: ['--disable-feature=parametersubstitution', '-DSYNTHESIS']
++      symbiflow:
++        package: "csg324-1"
++        part: "xc7a35t"
++        pnr: "vtr"
++        vendor: "xilinx"
++        surelog_options: ['--disable-feature=parametersubstitution', '-DSYNTHESIS']
 diff --git a/shared/fpga_xilinx.core b/shared/fpga_xilinx.core
 index 242f1f2d..26b05f1f 100644
 --- a/shared/fpga_xilinx.core
@@ -166,6 +125,3 @@ index 242f1f2d..26b05f1f 100644
      file_type: systemVerilogSource
 
  targets:
--- 
-2.33.1
-